US 5,845,107 A · Signaling protocol conversion between a processor and a high-performance system bus

Abstract

A method of operation in a computer system having a host processor, a pipelined system bus, and at least one agent, all of which operate in accordance with a first signaling protocol, and a processor that is included in a subsystem that operates according to a second signaling protocol which is incompatible with the first signaling protocol. The method comprises the steps of converting arbiter signals generated by the subsystem processor from the second signaling protocol to the first signaling protocol of the pipelined bus to obtain ownership of the pipelined bus. Next, an outgoing request encoding of the processor is translated from the second signaling protocol to the first signaling protocol. Finally, generating a bus cycle on the pipelined bus from the translated outgoing request encoding in accordance with the first signaling protocol of the pipelined bus.

Claims16

Dependent claims

In a computer system having a host processor, a pipelined system bus, and at least one bus agent, all of which operate in accordance with a first signaling protocol such that information transfer occurs across the pipelined bus between the host processor and the at least one bus agent, a method of operation with a subsystem that includes a processor operating according to a second signaling protocol which is incompatible with the first signaling protocol, the method comprising the steps of:

(a) converting arbiter signals generated by the processor from the second signaling protocol to the first signaling protocol to obtain ownership of the pipelined bus on behalf of the processor;
(b) translating an outgoing request encoding of the processor from the second signaling protocol to the first signaling protocol;
and
(c) generating a bus cycle on the pipelined bus from the translated outgoing request encoding.

1 more element

A bus conversion device for converting between a first signaling protocol associated with a standardized bus interface of a system bus in a host computer system and a second signaling protocol associated with a specific bus interface of a processor, the bus conversion device comprising:

a first request logic unit coupled between the standardized bus interface and the specific bus interface that converts bus request signals of the processor in the second signaling protocol to corresponding bus request signals of the standardized bus interface in accordance with the first signaling protocol;
arbitration logic unit coupled between the standardized bus interface and the specific bus interface that obtains ownership of the system bus on behalf of the processor according to an arbitration algorithm;
and
a second request logic unit coupled between the standardized bus interface and the specific bus interface that identifies a transaction on the system bus that is snoopable by the processor, and inputs the transaction to the processor.

1 more element

Dependencies are inferred from the claim text.

Signaling protocol conversion between a processor and a high-performance system bus

Life of this patent

Signaling protocol conversion between a processor and a high-performance system bus

Life of this patent

Abstract

Claims16