Method for simulating cache operation
AssigneeAdvanced Micro Devices, Inc.
InventorWarren G. Stapleton
Life of this patent
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Abstract
Multiple functional units of a computer system that typically access a secondary cache and the main memory system independently and simultaneously are simulated using RTL models which create such accesses using a random process. In one embodiment, an RTL model of each functional unit generates accesses to the cache memory according to a programmable frequency. The RTL models of these functional units also generate addresses which fall within programmable address limits and tag limits. In one embodiment, the functional units include data and instruction table lookaside buffers which traverse a two-level address translation scheme.
Claims11
A method for simulating, at the register transfer (RTL) level, a cache memory in a computer system having a plurality of functional units which access said cache memory and a main memory system, said method comprising the steps of:
- creating for said cache memory an RTL model;
- for each of said functional units, creating an RTL model capable of randomly generating (i) an access event to said cache memory at a programmable frequency, and (ii) an address for use with said access event;
- and
- at each simulation time period, invoking said RTL model of each of said functional unit to generate said access event probabilistically, and if said access event is generated, simulating access to said cache memory by submitting said address to said RTL model of said cache memory in simulated access of said cache memory.
Dependencies are inferred from the claim text.