Computer with dynamic instruction reuse
AssigneeWisconsin Alumni Research Foundation
InventorsAvinash Sodani, Gurindar S. Sohi
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Abstract
A computer architecture allowing reuse of previously determined instruction results, indexes instruction results according to instruction addresses. The continued validity of operand values in registers or memory for the instructions is determined prior to the fetching of any given instruction by an invalidation system which detects an intervening register or memory write. Thus, the need to evaluate the operand values themselves which would delay execution is avoided. In one embodiment, dependencies for operands between instructions are recorded so as to avoid invalidating instructions having operand register or memory locations which are overwritten when the overwriting will be corrected by an intervening instruction immediately preceding the dependent instructions.
Claims11
A computer for executing a program of instructions, the instructions including at least one operand, the instructions stored in memory at instruction addresses, the computer comprising:
- fetching circuitry, obtaining a fetched instruction from memory at a fetched instruction address;
- execution circuitry selectively executing fetched instructions to produce results;
- a reuse memory, communicating with the fetching circuitry, holding linked operand identifiers, results and indices based on instruction addresses of previously executed instructions;
- and
- search circuitry receiving the fetched instruction address and searching the reuse memory for a valid matching entry having an index matching the fetched instruction address and when a valid matching entry is found instructing the execution circuitry to bypass the execution of the fetched instruction and use the result of the matching entry.
Dependencies are inferred from the claim text.