Determining microcode entry points and prefix bytes using a parallel logic technique
AssigneeAdvanced Micro Devices, Inc.
InventorsPaul K. Miller, Rupaka Mahalingaiah
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AssigneeAdvanced Micro Devices, Inc.
InventorsPaul K. Miller, Rupaka Mahalingaiah
Estimating the term…
A superscalar microprocessor implements a microcode instruction unit with an MROM entry point generator. The MROM entry point generator generates the first address of a microcode sequence that effectuates the function of an MROM instruction. The address of the microcode instruction depends upon the prefix bytes, the opcode bytes and the ModR/M byte of the MROM instruction. To expedite the generation of the first address, or entry point address, a plurality of entry point address generators generate entry point addresses based on a presumed state of the prefix byte. In parallel with the generation of the entry point addresses, a prefix decoder decodes the prefix byte to determine the state of the prefix byte. The output of the entry point address generator that generated an entry point address based on the actual prefix byte is selected. By decoding the prefix byte in parallel with entry point address generation, the propagation delay associated generation of entry point addresses is advantageously reduced.
A microcode instruction unit comprising:
A method of accessing a microcode sequence that effectuates a function of a complex instruction comprising the steps of:
A microprocessor comprising:
Dependencies are inferred from the claim text.