Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache

An instruction buffer for storing instructions prior to their storage in an instruction cache of a microprocessor, comprising:

• an address buffer configured to store an address corresponding to a plurality of instruction bytes;
• an instruction data buffer configured to store said plurality of instruction bytes, wherein said instruction data buffer is coupled to receive said plurality of instruction bytes from a source external to said microprocessor;
• a control unit coupled to said instruction data buffer, wherein said control unit is configured to retain said plurality of instruction bytes within said instruction data buffer if an instruction fetching mechanism within said microprocessor initiates an instruction fetch for a second address dissimilar from said address stored in said address buffer;
• and
• a second control unit coupled to said address buffer, wherein said second control unit is coupled to receive a fetch address from said instruction cache, and wherein said instruction cache is concurrently searching for instruction bytes corresponding to said fetch address.

A microprocessor comprising:

• an instruction cache configured to store instructions;
• a prefetch/predecode unit coupled to receive a plurality of instruction bytes from an external source in response to a fetch miss in said instruction cache, wherein said prefetch/predecode unit is configured to retain said plurality of instruction bytes if said instruction cache fetches an address indicative of another plurality of instruction bytes;
• and
• an external interface unit coupled to said instruction cache and said prefetch/predecode unit, wherein said external interface unit is configured to store an address corresponding to said plurality of instruction bytes and to compare said address to a fetch address being concurrently searched within said instruction cache, and wherein said prefetch/predecode unit conveys said plurality of instruction bytes to an instruction processing pipeline of said microprocessor if said address matches said fetch address.