Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length

A circuit that receives an input block of instruction code at a circuit input and provides an output block of instruction code to an instruction decoder, said circuit comprising:

• a first instruction buffer, a second instruction buffer, and a bypass bus, each having an input coupled to said circuit input, the first and second instruction buffers capable of storing up to a maximum of N bytes of instruction code, wherein N is a predetermined number;
• a multiplexer having an input coupled to said first instruction buffer, said second instruction buffer, and said bypass bus;
• and
• a rotator coupled to receive greater than N bytes of instruction code from said multiplexer, said rotator providing to said instruction decoder said output block of instruction code comprising up to N bytes of instruction code aligned at an instruction boundary;
• wherein said input block of instruction code has instruction buffer qualification bits associated therewith, said instruction buffer qualification bits being passed through to said instruction decoder with said output block of instruction code.

A circuit that receives an input block of instruction code at a circuit input and provides an output block of instruction code to an instruction decoder, said circuit comprising:

• a first instruction buffer, a second instruction buffer, and a bypass bus, each having an input coupled to said circuit input, the first and second instruction buffers capable of storing up to a maximum of N bytes of instruction code, wherein N is a predetermined number;
• a multiplexer having an input coupled to said first instruction buffer, said second instruction buffer, and said bypass bus;
• and
• a rotator coupled to receive greater than N bytes of instruction code from said multiplexer, said rotator providing to said instruction decoder said output block of instruction code comprising up to N bytes of instruction code aligned at an instruction boundary;
• wherein each byte of said input block of instruction code has an auxiliary bit associated therewith, each said auxiliary bit being passed through to the instruction decoder with each byte of said output block of instruction code.

In a processor that executes variable-length instructions, a circuit that receives an input block of instruction code and provides an output block of instruction code to an instruction decoder, said circuit comprising:

• a first instruction buffer, a second instruction buffer, and a bypass bus, each coupled to receive said input block of instruction code, the first instruction buffer capable of storing a maximum of N bytes of data;
• a multiplexer coupled to receive an input from said first instruction buffer, said second instruction buffer, and said bypass bus, said multiplexer providing an intermediate output block of instruction code;
• a rotator coupled to receive up to 2.times.N bytes of the intermediate output block of instruction code from the multiplexer, the rotator providing the output block of instruction code to the instruction decoder;
• and
• pointer logic coupled to said rotator, said pointer logic for indicating an initial byte of an instruction, said rotator providing said output block of instruction code beginning with said initial byte of the instruction.

In a processor that executes variable-length instructions, a circuit that receives an input block of instruction code and provides an output block of instruction code to an instruction decoder, said circuit comprising:

• a first instruction buffer, a second instruction buffer, and a bypass bus, each coupled to receive said input block of instruction code, the first instruction buffer capable of storing a maximum of N bytes of data;
• a multiplexer coupled to receive an input from said first instruction buffer, said second instruction buffer, and said bypass bus, said multiplexer providing an intermediate output block of instruction code;
• and
• a rotator coupled to receive up to 2.times.N bytes of the intermediate output block of instruction code from the multiplexer, the rotator providing the output block of instruction code to the instruction decoder;
• wherein said input block of instruction code has instruction buffer qualification bits associated therewith, said instruction buffer qualification bits being passed through to said instruction decoder with said output block of instruction code.

In a processor that executes variable-length instructions, a circuit instruction decoder, said circuit comprising:

• a first instruction buffer, a second instruction buffer, and a bypass bus, each coupled to receive said input block of instruction code, the first instruction buffer capable of storing a maximum of N bytes of data;
• a multiplexer coupled to receive an input from said first instruction buffer, said second instruction buffer, and said bypass bus, said multiplexer providing an intermediate output block of instruction code;
• and
• a rotator coupled to receive up to 2.times.N bytes of the intermediate output block of instruction code from the multiplexer, the rotator providing the output block of instruction code to the instruction decoder;
• wherein each byte of said input block of instruction code has an auxiliary bit associated therewith, each said auxiliary bit being passed through to the instruction decoder with each byte of said output block of instruction code.

A method of providing a plurality of instruction code bytes via a circuit to an instruction decoder, the method comprising the steps of:

• (a) providing instruction code from a first buffer and a second buffer via a multiplexer to a rotator;
• (b) providing an output of the rotator comprising sequentially-addressed instruction code aligned at an instruction boundary to the instruction decoder, the sequentially-addressed instruction code having partially come from the first buffer and partially from the second buffer;
• and
• (c) providing a pointer to the rotator, the pointer indicating the instruction boundary of the step (b).