US 5,845,099 AGranted

Length detecting unit for parallel processing of variable sequential instructions

AssigneeIntel Corporation

InventorsNaveen Krishnamurthy, Nadeem H. Firasta

Life of this patent

Estimating the term…

Loading patent…

Abstract

A microprocessor with a circuit that selects at least one instruction from a stream of N successive instruction bytes. The circuit includes a first pointing unit that indicates a position of a first byte of an instruction of the stream of N successive instruction bytes. The circuit also includes a second pointing unit that stores a vector having a length N which indicates a position of a last byte of the instruction in the stream. The circuit further includes a first alignment unit coupled to the first and the second pointing units, the first alignment unit aligns the vector at a position indicating the first byte of an instruction. The circuit includes a first and a second length detecting units that receive the aligned vector in parallel. The first and second length detecting units simultaneously determine the length of a current instruction and the length of a next instruction, respectively, of the stream of N successive instruction bytes.

Claims18

Dependent claims

In a microprocessor of a type that includes instructions of variable length, a circuit to select at least one instruction from a stream of N successive instruction bytes, said circuit comprising:

a first pointing unit to indicate a position of a first byte of an instruction of said stream of N successive instruction bytes;
a second pointing unit to store a vector having a length N, said vector indicating a position of a last byte of at least one instruction of said stream of successive instruction bytes;
a first alignment unit coupled to said first and second pointing units, the first alignment unit aligns said vector at said position indicating said first byte of an instruction;
and
a first length detector to receive an aligned vector from said first alignment unit and to determine a length of a first instruction of said stream of N successive instruction bytes;
and
a second length detector to receive in parallel said aligned vector and to determine a sum of said length of said first instruction and of a length of a second instruction, said second length detector includes a plurality of units Ui, with i equal 1 to M, each unit Ui receives in parallel said aligned vector and responsive thereto generates a speculative sum of a speculative length of said first instruction and of a speculative length of said second instruction, each unit Ui assumes that said speculative length of said first instruction is equal to i.

4 more elements

In a microprocessor of a type that includes instructions of variable length, a circuit for selecting at least one instruction from a stream of N successive instruction bytes, said circuit comprising:

a first pointing unit that indicates a position of a first byte of said at least one instruction of said stream;
a second pointing unit that stores a vector having a length N, said vector indicates a position of a last byte of said at least one instruction of said stream;
a first alignment unit, coupled to said first and second pointing units, that aligns said vector at said position to indicate said first byte of said at least one instruction;
first and a second length detecting units that receive in parallel an aligned vector from said first alignment device and that simultaneously determines the lengths of a current and of a length of a next instruction, respectively;
an instruction buffer that stores said stream of N successive instructions bytes;
a second alignment unit, coupled to said first pointing unit and to said instruction buffer, that receives said stream of N successive instruction bytes and that aligns said stream of N successive instruction bytes according to said position of said first byte;
said first pointing device includes a first buffer for storing a read pointer indicating said position of said first byte of an instruction of said stream, said first buffer having an input and an output;
said second pointing device includes a second buffer for storing said vector and said vector includes N bits lockstepped to said N successive instruction bytes, said N bits having an active bit at a position corresponding to said position of said last byte of said at least one instruction;
said first alignment unit is a rotator that rotates said N bits by a number of bits equal to said read pointer and that outputs a subset of said N bits;
said first length detecting unit includes circuitry that detects a second occurrence of an active bit in said subset of N bits;
and
said second length detecting unit includes circuitry that deletes a second occurrence of an active bit in said subset of N bits.

9 more elements

Dependencies are inferred from the claim text.