Address lines load reduction

A method for operating a system having an address generator, an address bus, a bus controller, and multiple subsystems coupled by the address bus, the address bus including higher order address lines and lower order address lines, and wherein a first subsystem has a first subsystem select address and lower order address connections for receiving lower order addresses identifying an address space within the first subsystem, the method comprising:

• (a) operating the address generator coupled to the bus controller for providing addresses, including a subsystem select addresses and lower order addresses;
• (b) operating the bus controller to (i) receive the subsystem select addresses provided by the address generator and (ii) couple the lower order addresses from the address generator to a subset of the higher order address lines of the bus not used for subsystem select, when the subsystem select address from the address generator equals the first subsystem select address, but not when it equals a select address of another of the multiple subsystems.

A method for operating a system with more equally distributing bus line loading, said system having multiple peripherals using different numbers of address bits, said peripherals being served by a bus, said method comprising the steps of, dynamically mapping lower order internal address bits of at least one selected peripheral, but not of another selected peripheral, to higher order address lines of the bus that are not used to select the at least one selected peripheral, so that some lower address lines of the bus need not be loaded by the selected peripheral.