Adaptive arbitration mechanism for a shared multi-master bus

An arbitration method for determining which of plurality of peripheral components shall have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus comprising the steps of:

• a) recording all requests by a plurality of peripheral components for access to a PCI bus, and storing said recorded requests in a first-in-first-out (FIFO) history buffer, said FIFO history buffer records past usage of the PCI bus;
• b) determining which of said plurality of peripheral components requests access to said PCI bus most often;
• and
• c) granting said peripheral component which requests access to said PCI bus most often access to said PCI bus when no other of said plurality of peripheral components requests access to said PCI bus.

An system for adaptively arbitrating access to a peripheral component interconnect (PCI) bus comprising:

• an adaptive PCI bus arbitrating device configured to arbitrate access for plurality of peripheral components to a PCI bus, said adaptive PCI bus arbitrating device further comprising:
• a history buffer, said history buffer adapted to record requests from said plurality of peripheral components for access to said PCI bus;
• and
• a summation accumulator coupled to said history buffer for determining which of said plurality of peripheral components has the highest priority value for access to said PCI bus;
• a priority encoder coupled to said summation accumulator, said priority encoder granting to said peripheral component which has said highest priority value access to said PCI bus when no other of said plurality of peripheral components requests access to said PCI bus;
• and
• a weight buffer coupled to said history buffer and said summation accumulator, said weight buffer for adjusting said priority values of said requests recorded in said history buffer such that said determination by said summation accumulator of which of said plurality of peripheral components has said highest priority value for access to said PCI bus is affected by said weight buffer.