System for receiving a data stream of serialized data

A receiver for receiving at an input port a data stream of frames of serialized data over a high-level data-link, and for storing said received data until said data are read by a microprocessor, said receiver comprising:

• a state machine effectuated on a single integrated circuit for detecting frame opening flags, abort signals, and frame closing flags within said received data;
• for deleting non-data-carrying zeros;
• and for generating a gated clock signal when said receiver is in-frame;
• said state machine being controlled via hardware-based means;
• a shift register external to said state machine for converting said serialized data into parallel data;
• a cyclical redundancy check (CRC) checker external to said state machine for validating said frames of received data;
• and
• a two-word-deep first-in, first-out (FIFO) buffer external to said state machine for storing said parallel data until said data are read by said microprocessor, each word of said two-word-deep FIFO buffer including a data portion in addition to a first portion for an end-of-message indication, a second portion for an indication that said data portion is full and a third portion for an indication of an invalid data frame, wherein said state machine and said shift register are both connected directly to said input port, and wherein said CRC checker and said FIFO buffer are both connected to said shift register.

An instruction processor implemented on a single integrated circuit, said instruction processor comprising:

• a microprocessor;
• a high-level data-link controller (HDLC) receiver for receiving from a data port a data stream of frames of serialized data over a high-level data-link, and for storing said received data until said data are read by said microprocessor, said HDLC receiver comprising:
• a state machine formed on said integrated circuit for detecting frame opening flags, abort signals, and frame closing flags within said received data;
• for deleting non-data-carrying zeros;
• and for generating a gated clock signal when said receiver is in-frame;
• said state machine being controlled via hardware-based means;
• a shift register for converting said serialized data into parallel data;
• a cyclical redundancy check (CRC) checker for validating said frames of received data;
• and
• a two-word-deep first-in, first-out (FIFO) buffer for storing said parallel data until said data are read by said microprocessor, each word of said two-word-deep FIFO buffer including data portion in addition to a first portion for an end-of-message indication, a second portion for an indication that said FIFO buffer is full and a third portion for an indication of an invalid data frame, wherein said state machine and said shift register are both connected directly to said input port, wherein said CRC checker and said FIFO buffer are both connected to said shift register and wherein said state machine is coupled to a CRC checker for CRC receive function capability.