Method and apparatus for parallel and pipelining transference of data between integrated circuits using a common macro interface

A high-end parallel disk control system, comprising:

• a memory interface adapter coupled to and transferring data between a processor bus, an input/output port control register, dynamic memory, and a control bus;
• a processor coupled to the processor bus;
• a buffer interface adapter coupled to the control bus, and the input/output port control register;
• a link interface adapter and a system adapter coupled to the control bus, the link interface adapter for communicating with a disk drive system and the system adapter coupled to a communication link;
• a data bus disposed between the link interface adapter and the buffer interface adapter for facilitating the transference of data to and from the disk drive system;
• and
• the memory interface adapter, buffer interface adapter, link interface adapter and system adapter having slave and master macros for controlling and processing communications, the processing of communications being accomplished over a unique communication freeway disposed within each of the memory interface adapter, buffer interface adapter, link interface adapter and system adapter for providing parallel and pipelining processes, and a common macro interface providing a common communication protocol for requesting and acknowledging data and request transfers between the slave and master macros.

A system for parallel and pipelining transference of data between a plurality of integrated circuits, each of the plurality of integrated circuits having one or more slave and master macros for generating and processing requests, the system comprising:

• a unique communication network disposed within at least one of the integrated circuits for providing parallel and pipelining processes;
• and
• a common protocol interface disposed between the unique communication network and a respective one slave macro and a respective one master macro within the at least one of the integrated circuits, for providing a common communication protocol for requesting and acknowledging data and request transfers between the slave and master macros;
• and
• an arbiter disposed between the common macro interface and the respective one slave macro to prevent traffic collisions and locking of the network.

A method for parallel and pipelining transference of data between a plurality of integrated circuits each having one or more master and slave macros for processing data, the method comprising the steps of:

• providing a unique communication network within each of the integrated circuits;
• sending a request to a desired one of the slave macros from a particular one of the master macros;
• sending an address of the desired slave macro onto at least one of the communication networks;
• designating whether the request was a read operation or a write operation;
• routing the request to the address of the desired slave macro by one or more of the communication networks;
• providing a request acknowledgment signal in response to the desired slave macro receiving the request from the particular master macro;
• and
• providing a data acknowledgment signal from the desired slave macro, the data acknowledgment signal indicating that the data is ready if the operation was a read operation or that the desired slave macro received the data if the operation was a write operation.