High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors

A fault-tolerant computer system, comprising:

• a plurality of Central Processor Units (CPUs) each CPU having an independent clock for controlling the execution of instructions at a timing independent of the other CPUs, each CPU periodically issuing an I/O request for an input/output (I/O) operation after execution of plural instructions;
• means for receiving said periodic I/O requests from said plurality of CPUs and for voting said I/O requests;
• and
• CPU synchronization means, for each CPU, for controlling the clock length of said I/O operations of said CPUs, each said CPU synchronization means including:
• means for determining the number of clock cycles taken by each of said CPUs for said requested I/O operation,
• means for comparing the number of clock cycles to determine the longest clock length for said I/O operations, and
• means for controlling each of said CPUs to take said longest clock length for said I/O operation, the controlling means including compare logic for receiving the longest clock length of the I/O operations and subtracting a local CPU clock length from the longest clock length to obtain an I/O length difference amount, and further including logic that stalls the CPUs for the respective I/O length difference amount.

A fault-tolerant computer system for processing an instruction stream and for communicating with external devices, comprising:

• first, second and third Central Processor Units (CPUs) of substantially identical configuration, said first, second and third CPUs executing substantially the same instruction stream, each of said first, second and third CPUs having independent clocks, said clocks providing clock cycles for timing the execution of said instruction stream so that said execution is asynchronous between said CPUs over plural clock cycles;
• one or more memory modules;
• bus means, coupled to said first, second and third CPUs and to said one or more memory modules, for allowing access by said CPUs to said memory modules and to said external devices during CPU input/output (I/O) operations;
• synchronization means, in each CPU, for controlling the CPU during I/O operations so that an I/O operation takes the same amount of time for each of the CPUs, the CPU synchronization means including compare logic, for each CPU, for receiving a longest I/O length of the I/O operations and subtracting a local CPU I/O operation length from the longest I/O length to obtain an I/O length difference amount, and further including, for each CPU, logic that stalls the CPU for its I/O length difference amount;
• and
• means for periodically stalling said CPUs for a variable stall length between CPUs so as to substantially align said CPUs in real time.

A method for synchronizing a fault-tolerant computer system having a plurality of central processing units (CPUs) executing the same instruction stream at clock cycles provided independently for each of said CPUs, comprising the steps of:

• providing the local clock cycle of each CPU to each of the other CPUs;
• detecting a CPU I/O request for an I/O operation and providing a count initiating signal to initiate counting said local clock cycles in each of said CPUs;
• repeating said I/O request detecting and counting step for each of the CPUs such that each of said CPUs counts clock cycles for its local clock as well as the clocks of the other CPUs;
• detecting the end of the I/O operation and stopping said counting of clock cycles within each of the CPUs such that each CPU has an I/O count value corresponding to each of said CPUs;
• comparing said count values within each said CPU and determining the longest count value;
• determining for each of said CPUs the difference between the local count value and the longest count value and providing such difference as a wait count;
• stalling each of said CPUs for said CPU's wait count number of clock cycles;
• and
• releasing each of said CPUs to continue processing said instruction stream after completing said wait count stall;
• wherein each of said CPUs is forced to take the same number of clock cycles for said I/O operation.

A fault-tolerant computer system for processing an instruction stream, comprising:

• a plurality of processor modules, each of said processor modules executing said instruction stream and each having an independent clock for providing clock signals controlling the timing of execution of the instructions, wherein each of said processor modules periodically issues I/O requests for I/O operations and wherein said I/O requests occur asynchronously between said processor modules;
• and
• means for receiving said I/O requests and providing an acknowledge signal to said processor modules when said requested I/O operation is completed;
• wherein each processor module further includes synchronization means comprising:
• means for determining a length of the I/O operation for each of the respective processor modules,
• means for detecting an error in said I/O operation length for one or more of said processor modules,
• compare logic for receiving a longest I/O length of the I/O operations and subtracting a local processor module I/O length from the longest I/O length to obtain an I/O length difference amount, and
• logic that stalls the processor module for the I/O length difference amount.

A fault-tolerant computer system for processing an instruction stream, comprising:

• a plurality of processors in respective processor modules, each processor executing said instruction stream and each processor module having an independent clock for providing clock signals controlling the timing of execution of the instruction stream, wherein each of said processor modules periodically issues I/O requests for input/output (I/O) operations and wherein said I/O requests occur asynchronously between said processor modules;
• one or more external devices clocked separately from said processor modules and receiving the I/O requests from said processor modules;
• logic that couples said processor modules to said one or more external devices so that the I/O operations can be performed between said processor modules and said one or more external devices;
• processor synchronization logic, in each processor module, that controls the processor modules so that the I/O operation takes the same number of clock cycles for each processor module, the processor synchronization logic including, in each processor module, compare logic for receiving a longest I/O length of the I/O operations and subtracting a local processor module I/O length from the longest I/O length to obtain an I/O length difference amount, and further including logic that stalls the processor module for the I/O length difference amount.