Fine resolution digital delay line with coarse and fine adjustment stages

A digital delay line for inserting propagation delay into a signal path, comprising:

• a first delay circuit comprising a synchronous divide by circuit, a halfstep switching logic circuit, and an element circuit;
• a first input of said synchronous divide by circuit coupled to receive one of said two clock signals, a second input of said synchronous divide by circuit coupled to receive a clear signal;
• a first input of said halfstep switching logic circuit connected to a first output of said synchronous divide by circuit and to a first output of said first delay circuit, a second input of said halfstep switching logic circuit coupled to receive the other of said two clock signals, a third input connected to a second output of said synchronous divide by circuit and to a second output of said first delay circuit, a fourth input coupled to receive said clear signal, and a first output connected to a third output of said first delay circuit;
• and
• a first input of said element circuit connected to a data input of said first delay circuit, a second input connected to a second output of said halfstep switching logic and to a fourth output of said first delay circuit and an output connected to a fifth output of said first delay circuit, said first delay circuit providing delay adjustment of a first range;
• and
• a second delay circuit directly connected to said first delay circuit, said second delay circuit providing delay adjustment of a second range.

A digital phase locked loop circuit, comprising:

• a phase detector having first and second inputs for first and second clock signals to be applied respectively thereto;
• first delay circuitry connected to said phase detector for providing delay adjustment of a first range;
• and
• second delay circuitry having an input coupled to an output of said first delay circuitry an output coupled to said second input of said phase detector providing said second clock signal thereto, said second delay circuitry responsive to said phase detector and to said first delay circuitry for providing delay adjustment of a second range, a combination of said first and second delay circuitry providing a precise delay adjustment.

A digital phase locked loop circuit, comprising:

• a phase detector for detecting a phase relationship between first and second clock signals, said phase detector having first and second inputs for said first and second clock signals to be applied thereto;
• first delay circuitry directly connected to said phase detector for providing delay adjustment of a first range, said first delay circuitry comprising a first input connected to an output of said phase detector, a second input connected to a third input of said phase detector and coupled to receive a control signal and at least a third input connected to said first input of said phase detector receiving said first clock signal;
• and
• second delay circuitry responsive to said phase detector and to said first delay circuitry for providing delay adjustment of a second range, said second delay circuitry includes a first input connected to a first output of said first delay circuitry, a second input connected to a second output of said first delay circuitry, a third input connected to said third input of said phase detector, a fourth input connected to said output of said phase detector and an output connected to said second input of said phase detector, a combination of said first and second delay circuitry providing a precise delay adjustment.