Matched filter system
AssigneesKokusai Electric Corporation, Yozan Inc.
InventorsChangming Zhou, Guoliang Shou, Makoto Yamamoto, Kenzo Urabe, Sunao Takatori
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Abstract
The present invention solves the conventional problems and has an object to provide a matched filter system of high process in speed, a small size and low electric power consumption. The matched filter circuits of each matched filter set is allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, cyclically performs sampling every 1 chip time duration the input signals to be inputted to each set constructed by matched filter circuits by n sets each of which including n matched filter circuits, and calculates the sum of outputs of all matched filter circuits.
Claims18
A matched filter system for multiplying a predetermined PN code sequence to a plurality of spread spectrum signals of time series and calculating an accumulated value of them, comprising:
- i) n groups of matched filter sets each of which includes n matched filter circuits having M/n taps, said matched filter circuits of each said matched filter set being allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, said matched filter circuits of each said matched filter set being provided sampling clocks for sampling said spread spectrum signal of a period of n*Tc, said sampling clocks being staggered by an offset time of Tc for said matched filter circuits in each said matched filter set,
- where,
- M:
- length of said PN code sequence,
- n:
- a measure of M, and
- Tc:
- chip time duration of said matched filter circuit;
- ii) a plurality of addition circuits corresponding to said matched filter groups, each of which adds total outputs of said matched filters of one of said matched filter groups;
- and
- iii) a multiplexer for selectively outputting an output of said addition circuits.
A matched filter system for multiplying a predetermined PN code sequence to a plurality of spread spectrum signals of time series and calculating an accumulated value of them, comprising;
- i) n groups of matched filter sets each of which includes n matched filter circuits having taps and one matched filter having (M mod n) taps, said matched filter circuits of each said matched filter set being allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, said matched filter circuits of each said matched filter set being provided sampling clocks for sampling said spread spectrum signal of a period of n*Tc, said sampling clocks being staggered by an offset time of Tc for said matched filter circuits in each said matched filter set,
- where,
- M:
- number of PN codes of said PN code sequence,
- n:
- a measure of M,
- .right brkt-top. .left brkt-top.:
- a Gauss' notation, and
- Tc:
- chip time of said matched filter circuit;
- ii) a plurality of addition circuits corresponding to said matched filter groups, each of which adds total outputs of said matched filters of one of said matched filter groups;
- and
- iii) a multiplexer for selectively outputting an output of said addition circuits.
A matched filter system for multiplying a predetermined PN code sequence to a plurality of spread spectrum signals of time series and calculating an accumulated value of them, comprising:
- i) the first matched filter circuit with taps of a half number of PN codes of said PN code sequence, in which every other PN codes in said PN code sequence are applied to said taps;
- ii) the second matched filter circuit with other half number of PN codes than said PN codes applied to said first matched filter;
- iii) a clock generating circuit for generating two clocks of opposite phases to each other of a half frequency of a chip rate, as sampling clocks of said first and second matched filter circuits;
- and
- iv) an adder for adding outputs of said matched filter circuits.
Dependencies are inferred from the claim text.