Fast framing of nude ATM by header error check

Abstract

This invention provides a fast framing device that processes a stream of bytes and generates a signal for every byte clock that indicates whether a selected Asychronous Transfer mode cell boundary may be valid. The fast framing device generates a Cyclical Redundancy Code (CRC) corresponding to each byte from a input byte stream. The generated CRC is processed by an XOR tree that produces an output equivalent to processing the CRC code through five cycles of an CRC generator. The result of the XOR tree is XORed with a hexidecimal number "AC" or 0.times.AC. The result of the XOR tree and the XOR gate is delayed by five cycles and then compared with the CRC generated during the fifth byte clock. The compared results indicate whether the prior five bytes may be a valid ATM cell header.

Dependencies are inferred from the claim text.