Method for testing word line leakage in a semiconductor memory device

A method for testing a semiconductor memory device having a plurality of memory cells that are arranged essentially in a matrix form which includes word lines and y-selection signal lines arranged essentially in rows and columns, respectively and wherein desired memory cells of the plurality of memory cells are selected by enabling one of said word lines and at least one of said plurality of y-selection signal lines, the method comprising the steps of:

• applying a desired voltage from a voltage source to said one of said word lines by electrically connecting the voltage source to the one of said word lines;
• removing after the step of applying, the electrical connection between the voltage source and the one of said word lines;
• after a predetermined period of time from the applying step, enabling said y-selection signal line for substantially simultaneously selecting a plurality of memory cells and then writing data into the selected plurality of memory cells;
• and
• reading from the selected plurality of memory cell the written data and checking the read-out data.

A method for testing a semiconductor memory device having a plurality of memory cells that are arranged essentially in a matrix form which includes word lines and y-selection signal lines arranged essentially in rows and columns, respectively and wherein desired memory cells of the plurality of memory cells are selected by enabling one of said word lines at least one of said and plurality of y-selection signal lines, the method comprising the steps of:

• reading data from the selected desired memory cells and writing data into the selected desired memory cells;
• applying a desired voltage from a voltage source to said one of said word lines by electrically connecting the voltage source to the one of said word lines;
• removing, after the step of applying, the electrical connection between the voltage source and the one of said word lines;
• after a predetermined period of time from the applying step, enabling said y-selection signal line for substantially simultaneously selecting a plurality of memory cells and then writing data into the selected plurality of memory cells;
• and
• reading from the selected plurality of memory cell the written data and checking the read-out data.