Test circuit and method for refresh and descrambling in an integrated memory circuit

A test method for a semiconductor integrated circuit having a test circuit section and a memory circuit section, the test method comprising the steps of:

• calculating a refresh point address based upon a time period required to complete a predetermined test algorithm on the memory circuit section and a predetermined refresh time required to maintain data stored in the memory circuit section;
• generating a test address and test data for testing a cell in the memory circuit section;
• comparing the test address with the refresh point address;
• holding the test address when the test address matches the refresh point address;
• performing a refresh operation to refresh the data stored in memory circuit section beginning with the refresh point address when the test address matches the refresh point address;
• and
• resuming the test algorithm at the test address after termination of the refresh operation.

A test method for a semiconductor integrated circuit having a test circuit section and a memory circuit section, wherein the memory circuit section includes logic for scrambling an address and a data signal input to the memory circuit section, the test method comprising the steps of:

• generating a test address and test data for testing a cell in the memory circuit section;
• descrambling the test address before inputting the test address into the memory circuit section;
• and
• descrambling the test data before inputting the test data into the memory circuit section.

A semiconductor integrated circuit, the circuit comprising:

• a memory circuit section having an address scrambling circuit adapted to scramble an input address signal, a data scrambling circuit adapted to scramble an input data signal, and a memory cell array adapted to store scrambled data output from the data scrambling circuit in cells corresponding to scrambled addresses output from the address scrambling circuit;
• and
• a test circuit section coupled to the memory circuit section and further comprising:
• an address counting circuit adapted to sequentially count a test address for testing said memory circuit section;
• an address descrambling circuit adapted to descramble the test address output from the address counting circuit to produce a descrambled test address which is output as the input address signal to the address scrambling circuit of the memory circuit section such that the test address matches the address of the memory cell array;
• a data generating circuit adapted to generate test data for testing the memory circuit section;
• a data descrambling circuit adapted to descramble the test data output from the data generating circuit to produce the input data signal to the memory circuit section such that the test data matches the data stored in the memory cell array for a given test address;
• and
• a built-in self test (BIST) control circuit being enabled by an external test enable signal, and operating in response to an external clock signal, wherein the BIST control circuit executes a test algorithm on the memory circuit section by controlling said address counting circuit and said data generating circuit in accordance with the test algorithm.