US 5,844,912 AGranted

Fast verify for CMOS memory cells

AssigneeAdvanced Micro Devices, Inc.

InventorBradley A. Sharpe-Geisler

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Abstract

A method of verifying functionality of a circuit including an array of CMOS memory cells, each memory cell including: an NMOS transistor and a PMOS transistor having a common floating gate and drains connected together to form an output; a control capacitor having a first terminal connected to the common floating gate; a first transistor having a source to drain path connecting a second terminal of the control capacitor to a control gate (CG) node and having a gate forming a wordline (WL) node; and a tunneling capacitor connecting a write control (WC) node to the common floating gate, wherein a row of memory cells in the array have CG nodes connected together and wherein a column of memory cells in the array have CG nodes connected together, the method including the steps of: (a) programming all memory cells in a selected row (b) applying V.sub.VER (.apprxeq.1.8V) to the CG and WC nodes of the cells in the selected row while applying a voltage V.sub.VER.spsb.+ (V.sub.VER plus an NMOS threshold) to WL nodes; (c) raising the WL nodes of selected cells in the selected row to V.sub.MUXVER.spsb.+ (V.sub.MUXVER.spsb.+ being V.sub.MUXVER or .apprxeq.6V plus an NMOS threshold); (d) lowering the WL nodes of unselected cells to V.sub.VER.spsb.+ ; and (e) raising the CG nodes of the selected cells to V.sub.MUXVER so that selected cell outputs go low . Once functional verification is performed with selected cells as chosen in steps (a-e), the selected cells are charged and steps (b-e) are repeated until all desired patterns of cells in the selected row have been selected in a functional verification process. Steps (a-e) are then repeated for a next selected row. The process of the present invention enables toggling the output of the selected cells from a programmed or low state to a high state without requiring that the selected cell be reprogrammed.

Claims4

Dependent claims

A method of verifying functionality of a circuit, the circuit including an array of memory cells, each memory cell including:

an NMOS transistor and a PMOS transistor having a common floating gate and drains connected together to form an output;
a control capacitor having a first terminal connected to the common floating gate;
and a first transistor having a source to drain path connecting a second terminal of the control capacitor to a control gate (CG) node and having a gate forming a wordline (WL) node, wherein a row of the memory cells in the array have CG nodes connected together, and wherein a column of the memory cells in the array have WL nodes connected together, the method comprising the steps of:
(a) selecting a row in the array of memory cells;
(b) programming memory cells in the selected row by applying at least a programming pulse V.sub.PP to the CG node of the cells in the selected row, wherein programming results in each memory cell in the selected row having an output which should be in a first state when a voltage V.sub.VER is applied to the CG node of each cell in the selected row while a voltage is applied to the WL node of the cell sufficient to provide a current path from the CG node to the first terminal of the control capacitor in the cell, V.sub.VER being sufficient to turn on both the PMOS and NMOS transistors of the cell if zero charge were stored on the floating gate of the cell;
(c) selecting at least one cell in the selected row;
(d) applying a voltage to the CG nodes of the cells in the selected row while applying a voltage to the WL nodes of the cells in the selected row to pass the voltage V.sub.VER to the second terminal of the control capacitor of the cells in the selected row;
(e) providing a voltage on the WL nodes of the at least one selected cell in the selected row to a voltage sufficient to turn on the first transistor in the at least one selected cell to pass a voltage V.sub.MUXVER from the CG node of the at least one selected cell;
(f) lowering the voltage on the WL nodes of unselected cells in the selected row sufficient to turn off the first transistor so that it does not pass V.sub.MUXVER in the unselected cells;
and
(g) raising voltage on the CG nodes of the cells in the selected row to provide V.sub.MUXVER to the second terminal of the control capacitor, V.sub.MUXVER being altered from V.sub.PP, but remaining sufficient so that the output of the at least one selected cell should be in a second state.

8 more elements

A method of verifying functionality of a circuit, the circuit including an array of memory cells, each memory cell including:

an NMOS transistor and a PMOS transistor having a common floating gate and drains connected together to form an output;
a control capacitor having a first terminal connected to the common floating gate;
a first transistor having a source to drain path connecting a second terminal of the control capacitor to a control gate (CG) node and having a gate forming a wordline (WL) node;
and a tunneling capacitor connecting a write control (WC) node to the common floating gate, wherein a row of the memory cells in the array have CG nodes connected together and WC nodes connected together, and wherein a column of the memory cells in the array have WL nodes connected together, the method comprising the steps of:
(a) programming a pattern of selected cells in each row in the array of cells by applying at least a programming pulse (V.sub.PP) to the CG nodes while applying V.sub.SS to the WC node of a cell to be programmed, wherein programming results in a memory cell having an output which should be at V.sub.SS when a voltage (V.sub.VER) is applied to the CG and WC nodes of the cell and a voltage is applied to the WL node of the cell sufficient to provide a current path from the CG node to the first terminal of the control capacitor in the cell, V.sub.VER being sufficient to turn on both the PMOS and NMOS transistors of the cell if zero charge were stored on the floating gate of the cell;
(b) selecting a row in the array of memory cells;
(c) programming the selected row;
(d) applying a voltage to the CG and WC nodes of the cells in the selected row while applying a voltage to the WL nodes of the cells in the selected row to pass the voltage V.sub.VER to the second terminal of the control capacitor of the cells in the selected row;
(e) providing a voltage on the WL nodes of the at least on selected cell in the selected row wherein the voltage is sufficient to turn on the first transistor in the at least one selected cell to pass a voltage V.sub.MUXVER from the CG node of the at least one selected cell;
(f) lowering the voltage on the WL nodes of the unselected cells in the selected row sufficient to turn off the first transistor so that it does not pass V.sub.MUXVER in the unselected cells;
and
(g) raising voltage on the CG nodes of the selected cells in the selected row to provide V.sub.MUXVER to the second terminal of the control capacitor, V.sub.MUXVER being lower than V.sub.PP, but remaining sufficient so that the output of the at least one selected cell should be at Vcc;
(h) determining if all columns in the selected row have previously included a selected cell and if not proceeding to step (i) and if so proceeding to step (j);
(i) column shifting the at least one selected cell so that the at least one selected cell occupies at least one other column which has not been previously selected and proceeding to step (d);
(j) erasing the cells in the selected row;
(k) reprogramming the pattern of selected cells previously programmed in the selected row;
(l) determining if all the rows in the memory array have been previously selected and if not proceeding to step (m);
(m) changing the selected row in the array of memory cells to another row which has not previously been selected and proceeding to step (c).

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/831,372Filed 1 Apr 1997
Granted: 1 Dec 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
G11C 29/50
Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals: marginal testing, e.g. race, voltage…
G11C 16/04
Electrically programmable: using variable threshold transistors, e.g. FAMOS
G11C 2029/5004
Marginal testing, e.g. race, voltage or current testing: voltage