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AssigneeInternational Business Machines Corporation
InventorsHideto Niijima, Takashi Toyooka, Akashi Satoh, Yoshinori Sakaue
Estimating the term…
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.
A nonvolatile semiconductor storage device with a flash erase capability comprising at least one array of memory cells whose operating voltages are supplied by means of word lines and bit lines, wherein memory cells sharing a word line are grouped into a first area manufactured in a first well of a semiconductor substrate and a second area manufactured in a second well of said semiconductor substrate, and said first well and said second well being physically and electrically isolated;
A nonvolatile semiconductor storage device with a flash erase capability comprising at least one array of memory cells whose operating voltages are supplied by means of word lines and bit lines, wherein memory cells sharing a word line are grouped into a first area and a second area such that particular contents of data stored in the memory cells of said second area are maintained when data stored in the memory cells of said first area are erased en bloc by applying an electric field between said word lines and the memory cells of said first area as a single voltage charge pulse to the memory cells of said first area, the memory cells of said first area including a first plurality of memory cells logically grouped into regular blocks that are usually employed for the storage of data, and a second plurality of memory cells logically grouped into redundant blocks that are employed for block replacement;
Dependencies are inferred from the claim text.