Test pattern selection method for testing of integrated circuit

A test pattern selection method for testing of an integrated circuit wherein, from within a test pattern file which includes L test patterns for testing of an integrated circuit, N test patterns designated as selection patterns are selected, L being an integer equal to or larger than 2, N being a positive integer smaller than L, comprising:

• the pattern reading step of reading out N test patterns as a set of temporarily selected patterns from the L test patterns in the test pattern file;
• the first fault rate calculation step of calculating a fault coverage of the combination of the N temporarily selected patterns;
• the second fault rate calculation step of successively substituting one of the other test patterns into one of the N temporarily selected patterns and calculating a fault coverage for each combination of test patterns;
• and
• a test pattern determination step for determining N test patterns of a combination which exhibits the highest one of the fault coverages calculated in the first fault rate calculation step and the second fault rate calculation step as finally selected patterns.