US 5,844,908 A · Digital delay system and method for digital cross connect telecommunication systems

Abstract

A system and method for provides a generating a plurality of clock phases from a clock signal in a telecommunications cross connect system. The digital delay circuit includes a plurality of delay elements connected in series, each delay element connected to a sampling element, the output of the sampling elements sent to a multiplexor. The total number of delay elements comprises a number that produces a worst case delay equal to or greater than the period of the clock signal. The delay elements receive the rising edge of the clock signal. The delayed rising edges are sent to the sampling elements. The sampling elements send outputs to the multiplexor for determining the number of delay elements transitions by one cycle of the clock signal. A programming device can be coupled to the multiplexor to request from the multiplexor a particular phase of the clock signal. The multiplexor can select the appropriate delay device to generate the particular phase of the clock signal.

Claims20

Dependent claims

A digital delay circuit in a digital cross connect telecommunications system for generating a plurality of clock phases from a clock signal, the digital delay circuit comprising:

a plurality of delay elements connected in series operable to receive a rising edge of the clock signal, the total number of delay elements comprising a number that produces a worst case delay equal to or greater than the period of the clock signal;
a plurality of sampling elements connected in series operable to receive the clock signal, each sampling element further connected to a delay element and further operable to sample that delay element;
a multiplexor connected to each sampling element and operable to receive and compare the output of each sampling element to determine the number of delay elements transitions by one cycle of the clock signal;
and
a programming device coupled to the multiplexor and operable to receive a request for a particular phase of the clock signal to be generated, divide the number of delay devices transitioned by the binary number representing the requested phase to determine an appropriate delay device at which that phase exists, and instruct the multiplexor to select the appropriate delay device so that the multiplexor generates the requested phase.

2 more elements

A digital delay circuit for use in a digital cross connect telecommunications system using a clock signal, comprising:

a plurality of delay elements connected in series operable to receive a rising edge of the clock signal, the total number of delay elements comprising a number that produces a worst case delay equal to or greater than the period of the clock signal;
a plurality of sampling elements connected in series operable to receive the clock signal, each sampling element further connected to a delay element and further operable to sample that delay element;
and
a multiplexor connected to each sampling element and operable to receive and compare the output of each sampling element to determine the number of delay elements transitions by one cycle of the clock signal.

1 more element

A method for generating a plurality of requested clock phases from a single clock signal in a digital cross connect telecommunications system using a digital delay circuit, the method comprising:

injecting the rising edge of the clock signal into a plurality of delay elements connected in series such that the delay elements produce a worst case delay equal to or greater than the period of the clock signal;
injecting the clock signal into a plurality of sampling elements connected in series;
sending the output of each delay element to an associated sampling element;
sending the output of the plurality of sampling elements to a multiplexor;
determining from the output of the plurality of sampling elements the number of delay elements transitioned by one cycle of the clock signal;
requesting a particular phase of the clock signal;
dividing the number of delay elements by a binary number representing the phase of the requested clock signal to determine the appropriate delay device from which to retrieve the requested phase;
selecting the appropriate delay device with the multiplexor to generate the requested clock phase as an output from the multiplexor.

5 more elements

Dependencies are inferred from the claim text.

Digital delay system and method for digital cross connect telecommunication systems

Life of this patent

Digital delay system and method for digital cross connect telecommunication systems

Life of this patent

Abstract

Claims20