Synchronous semiconductor memory device reliably fetching external signal in synchronization with clock signal periodically supplied from the exterior
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHisashi Iwamoto, Yasuhiro Konishi
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Abstract
When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.
Claims15
A synchronous semiconductor memory device comprising:
- storage means for continuously writing data of several bits being inputted from an exterior in synchronization with a clock signal every predetermined bit number and continuously reading said data in synchronization with said clock signal every said predetermined bit number;
- and
- control means for increasing a write period for said data by a predetermined time in response to increase of an operating frequency being the frequency of said clock signal within the range of a latency thereby controlling write and read operations for said data, said latency corresponding to the cycle number of said clock signal up to reading of first-bit data among said data after a read command is inputted from said exterior.
A synchronous semiconductor memory device continuously writing data of several bits being inputted from an exterior in synchronization with an external clock signal every predetermined bit number and writing said data in synchronization with said external clock signal every said predetermined bit number, said synchronous semiconductor memory device comprising:
- a storage portion for writing said data and reading said data;
- and
- a write operation ending control circuit for delaying ending of an operation for writing said predetermined bit-numbered data in said storage portion by a predetermined time when a latency corresponding to the cycle number of said external clock signal up to reading of first-bit data among said data is set at a second latency being longer than a first latency after a read command is inputted from said exterior.
A synchronous semiconductor memory device continuously writing data of several bits being inputted from an exterior in synchronization with an external clock signal every predetermined bit number and writing said data in synchronization with said external clock signal every said predetermined bit number, said synchronous semiconductor memory device comprising:
- a storage portion for writing said data and reading said data;
- and
- a control circuit for writing said data in said storage portion in a second write period being longer than a first write period for said data, said first write period being necessary when said clock signal corresponds to an external clock signal being inputted from an exterior, when said clock signal corresponds to a double clock signal of said external clock signal.
Dependencies are inferred from the claim text.