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AssigneeSamsung Electronics Co., Ltd.
InventorsMoon-hae Son, Jin-man Han
Estimating the term…
A row address control circuit for a memory device includes a row address enable signal generator, a row address buffer, a row predecoder, a row address strobe buffer, a predecoded row address sampling pulse generator, and a row decoder. The row address enable signal generator produces a row address enable signal which is enabled while a clock signal is enabled. The row address buffer receives the output of the row address enable signal generator and produces a row address signal enabled while the row address enable signal is enabled. The row predecoder receives and predecodes the output of the row address buffer and produces a predecoded row address signal. The row address strobe buffer receives the clock signal and produces a first control signal while the clock signal is enabled. The predecoded row address sampling pulse generator receives the output of the row address strobe buffer and produces a predecoded row address sampling pulse signal for selecting the predecoded row address signal while the first control signal is enabled. The row decoder receives the output of the predecoded row address sampling pulse generator and the row predecoder and has its output connected to a word line and activates the word line when the predecoded row address signal and the predecoded row address sampling pulse signal are enabled.
A row address control circuit for a memory device comprising:
A row address control circuit for a memory device, comprising:
A row address control method for a memory device comprising the steps of:
Dependencies are inferred from the claim text.