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US 5,844,856 AGranted
Dual port memories and systems and methods using the same
AssigneeCirrus Logic, Inc.
InventorRonald T. Taylor
Life of this patent
Estimating the term…
Abstract
A memory 20 includes a first array 100 and a second array 102 of memory cells. A first data port 118 allows for the exchange of data with the first array 100 and a second data port 120 allows for the exchange of data with the second array 102. Memory system 20 also includes a circuitry 122 for controlling data exchanges in a selected mode with the first array 100 via the first data port 118 and with the second array 102 via the second data port 120, the exchanges with the first and second arrays 100 and 102 being asynchronous.
Claims22
A memory system comprising:
- a first array of memory cells;
- a second array of memory cells;
- a first parallel data input/output port for exchanging data with said first array;
- a second parallel data input/output port for exchanging data with said second array;
- and
- circuitry for controlling data exchanges in a selected mode with said first array via said first data port and with said second array via said second data port, said exchanges between said first port and said first array and said second port and second array being independently control by corresponding first and second sets of addresses and control signals.
3 more elements
An I/O subsystem device comprising:
- a subsystem control circuit, said control circuit including a first control port for receiving a first set of addresses and control signals and a second control port for receiving a second set of addresses and control signals;
- first and second arrays of memory cells organized in rows and columns, each said row associated with a wordline and each said column associated with a bitline;
- a transfer gate disposed between a said bitline of said first array and a corresponding one of said bitlines of said second array, said transfer gate controlled by said subsystem control circuit;
- a first parallel data input/output port for exchanging data with said first memory array;
- a second parallel data input/output port for exchanging data with said second memory array;
- and
- wherein said I/O subsystem is operable in a first mode to provide independent access to said first and second arrays through said first and second data ports in response to independent sets of addresses and control signals presented at said first and second control ports and in a second mode to transfer data from selected cells of a selected one of said arrays to an other one of said arrays in response to addresses and control signals presented at a selected one of said control ports.
4 more elements
An I/O subsystem device for use in a processing system having first and second buses comprising:
- a subsystem control circuit operatively connected to said first and second buses;
- a subsystem memory operatively connected to said subsystem controller, said first bus, and said second bus including:
- a first array of memory cells having wordlines and bitlines;
- a second array of memory cells having wordlines and bitlines;
- a transfer gate coupled between each of said bitlines of said first array and corresponding ones of said bitlines of said second array, and coupled to said subsystem control circuitry;
- a first row decoder coupled between said subsystem control circuitry and said wordlines of said first array;
- a second row decoder coupled between said subsystem control circuitry and said wordlines of said second array;
- a first column decoder coupled between said subsystem control circuitry and said bitlines of said first array;
- a second column decoder coupled between said subsystem control circuitry and said bitlines of said second array;
- a first parallel data input/output port coupled to said first column decoder for exchanging data with said first device;
- a second parallel data input/output port coupled to said second column decoder for exchanging date with said second device;
- said subsystem control circuitry including:
- a first array controller coupled to said first column decoder and said first row decoder;
- and
- a second array controller coupled to said second column decoder and said second row decoder;
- whereby said first and second array controllers selectively allow independent accesses to said first and second memory arrays in response to corresponding first and second sets of addresses and control signals during a first mode via said first and second data ports.
13 more elements
A method of operating of memory device including first and second array of memory cells comprising the steps of:
- during a first mode:
- independently accessing the first array through a first data port in response to addresses and control signals received at a first control port;
- and
- independently accessing the second array through a second data port in response to addresses and control signals received at a second control port;
- and
- during a second mode:
- transferring data from bitlines of said first array to said bitlines second array in response to addresses and control signals received at a selected one of the first and second control ports said data driven from said bitlines of said fist array to said bitlines of said second array by sense amplifiers coupled to said bitlines of said first array.
4 more elements
Dependencies are inferred from the claim text.