Method and apparatus for writing to memory components

A method for writing data to a memory component having an array of storage cells arranged in rows and columns, comprising the steps of:

• the memory component initially receiving on its address lines a row address specifying a row in the storage array to be sensed and held in a set of sense amplifiers;
• and
• the memory component subsequently performing a first bit masked write operation comprising the steps of:
• the memory component receiving on address lines a first column address specifying a first column in the storage array;
• the memory component receiving first write data on data lines during the receiving of the first column address;
• the memory component receiving a first bit mask on the data lines prior to the receiving of the first write data;
• and
• writing the first write data into the array starting at the received first column address in accordance with the first bit mask.

A method for writing data to a memory component having an array of storage cells arranged in rows and columns, comprising the steps of:

• the memory component initially receiving on its address lines a row address specifying a row in the storage array to be sensed and held in a set of sense amplifiers;
• and
• the memory component subsequently performing a first bit masked write operation comprising the steps of:
• the memory component receiving on address lines a first column address specifying a first column in the storage array;
• the memory component receiving a first bit mask on data lines during the receiving of the first column address;
• the memory component receiving first write data on the data lines prior to the receiving of the first bit mask;
• and
• writing the first write data into the array starting at the received first column address in accordance with the first bit mask.

A memory device comprising:

• a memory array having rows, columns, and a plurality of sense amplifiers;
• means for receiving a row address specifying a row in the memory array to be sensed and held in the plurality of sense amplifiers;
• a memory interface coupled to the memory array and for performing a bit masked write operation after the receiving means receives the row address, the memory interface comprising:
• means for concurrently receiving a column address specifying a column in the memory array and write data;
• means for receiving a bit mask prior to the receiving of the write data;
• and
• means for writing the write data into the memory array starting at the received column address in accordance with the bit mask.

A memory device comprising:

• a memory array having rows, columns, and a plurality of sense amplifiers;
• means for receiving a row address specifying a row in the memory array to be sensed and held in the plurality of sense amplifiers;
• a memory interface coupled to the memory array and for performing a bit masked write operation after the receiving means receives the row address, the memory interface comprising:
• means for concurrently receiving a column address specifying a fist column in the memory array and a bit mask;
• means for receiving write data prior to the receiving of the bit mask;
• and
• means for writing the write data into the memory array starting at the received column address in accordance with the bit mask.

A method for writing data to a memory component having a static storage array of static storage cells arranged in rows and columns, comprising the steps of:

• the memory component receiving on its address lines a row address specifying a row in the static storage array to be sensed and held in a set of sense amplifiers;
• and
• the memory component performing a bit masked write operation comprising the steps of:
• the memory component receiving on address lines a column address specifying a column in the static storage array;
• the memory component receiving write data on data lines during the receiving of the column address;
• the memory component receiving a bit mask on the data lines prior to the receiving of the write data;
• and
• writing the write data into the static storage array starting at the received column address in accordance with the bit mask.

A method for writing data to a memory component having a static storage array of static storage cells arranged in rows and columns, comprising the steps of:

• the memory component receiving on its address lines a row address specifying a row in the static storage array to be sensed and held in a set of sense amplifiers;
• and
• the memory component performing a bit masked write operation comprising the steps of:
• the memory component receiving on address lines a column address specifying a column in the static storage array;
• the memory component receiving a bit mask on data lines during the receiving of the column address;
• the memory component receiving write data on the data lines prior to the receiving of the bit mask;
• and
• writing the write data into the static storage array starting at the received column address in accordance with the bit mask.

A memory system, comprising:

• a memory array having address inputs, a number of mask inputs, and a number of data inputs;
• and
• a memory interface, coupled to the memory array, for issuing a row address to the address inputs to sense a row of data in the memory array;
• the memory interface comprising:
• (i) a register, and
• (ii) control circuitry coupled to the register, the mask inputs, and the data inputs, the control circuitry configured to store in the register a selected one of a bit mask and write data to be written to the memory array, the register storing the bit mask in a first operating mode, and the write data in a second operating mode,
• the control circuitry also configured to issue the bit mask to the mask inputs from either a data bus or the register and configured to issue the write data to the data inputs from either the data bus or the register in order to write the write data to the sensed row of data in accordance with the bit mask.