Memory arrays with integrated bit line voltage stabilization circuitry
AssigneeIntel Corporation
InventorsRobert J. Murray, Paul D. Madland
Life of this patent
Estimating the term…
Abstract
The precharged bit lines of a memory array are provided with corresponding pass gate devices and a common complementary regulation and control circuitry to keep the precharged bit lines at a voltage below a first voltage and to counter-act any leakage to Vcc through a small current drain to a reference voltage. As a result, the voltage on the precharged bit lines are prevented from moving closer to Vcc, even during a prolonged idle period, and failure will not occur, when the memory cells are accessed again after the prolonged idle period.
Claims18
An apparatus comprising a memory array having columns of memory cells for storing data, a plurality of precharged bit line pairs correspondingly coupled to the memory cells for facilitating reading from and writing into the memory cells, and a bit line voltage stabilization circuit coupled to the precharged bit line pairs for keeping voltage on the precharged bit line pairs below a first voltage level during an idle period, and to counter-act any leakage to Vcc through a small current drain to a reference voltage during the idle period.
A single integrated circuit comprising
- a memory array having columns of memory cells for storing data, a plurality of precharged bit line pairs correspondingly coupled to the memory cells for facilitating reading from and writing into the memory cells, and a bit line voltage stabilization circuit coupled to the precharged bit line pairs for keeping voltage on the precharged bit line pairs below a first voltage level during an idle period, and to counter-act any leakage to Vcc through a small current drain to a reference voltage during the idle period;
- and
- access circuitry coupled to the memory array for accessing data stored in the memory array.
A digital component comprising
- a memory array having columns of memory cells for storing data, a plurality of precharged bit line pairs correspondingly coupled to the memory cells for facilitating reading from and writing into the memory cells, and a bit line voltage stabilization circuit coupled to the precharged bit line pairs for keeping voltage on the precharged bit line pairs below a first voltage level during an idle period, and to counter-act any leakage to Vcc through a small current drain to a reference voltage during the idle period;
- and
- a microcontroller coupled to the memory array for accessing data stored in the memory array.
A computer system comprising
- a memory array having columns of memory cells for storing data, a plurality of precharged bit line pairs correspondingly coupled to the memory cells for facilitating reading from and writing into the memory cells, and a bit line voltage stabilization circuit coupled to the precharged bit line pairs for keeping voltage on the precharged bit line pairs below a first voltage level during an idle period, and to counter-act any leakage to Vcc through a small current drain to a reference voltage during the idle period;
- and
- a processor coupled to the memory array for accessing data stored in the memory array.
Dependencies are inferred from the claim text.