US 5,844,851 A · Anti-noise and auto-stand-by memory architecture

Abstract

Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

Claims10

Dependent claims

A method for preventing spurious memory readings from a memory device caused by noise induced by transitions in an output buffer driven by a circuit capable of storing data extracted from a memory matrix of the memory device, said data storing circuit being in a disabled state during a propagation delay, in the memory device the method comprising the steps of:

upon a transition of memory address signals, replicating through a dummy chain the propagation delay of the transition of memory address signals through the memory device in producing new data;
and
enabling said data storing circuit to store the new data by means of an enabling pulse which is generated only after the replicated propagation delay.

Dependencies are inferred from the claim text.

Anti-noise and auto-stand-by memory architecture

Life of this patent

Anti-noise and auto-stand-by memory architecture

Life of this patent

Abstract

Claims10