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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKiyohiro Furutani
Estimating the term…
A semiconductor memory device includes a delay stage for delaying a row address strobe signal ZRAS by a predetermined time, a first signal generating circuit for generating a signal instructing activation/precharge of an array in accordance with the row address strobe signal ZRAS, and a second signal generating circuit for generating a signal setting the output stage to an output high impedance state in accordance with a delayed row address strobe signal ZRAS from the delay stage and a column address strobe signal ZCAS. Even if both the column address strobe signal and row address strobe signal may be simultaneously set to the high and low levels, respectively, the column address strobe signal and the delayed row address strobe signal are not simultaneously set to the high level, so that the output stage is prevented from attaining the high impedance state, and data output is allowed. Therefore, the semiconductor memory device can operate fast with a low current consumption.
A semiconductor memory device incorporating an external address signal to access a memory cell in accordance with the external address signal in a first cycle and subsequently accessing another memory cell in accordance with a count produced from a counter performing a counting operation with said external address signal being as a start address, comprising:
A semiconductor memory device having a plurality of memory cells arranged in rows and columns, comprising:
Dependencies are inferred from the claim text.