Method and Nonvolatile semiconductor memory for repairing over-erased cells

A nonvolatile semiconductor memory, comprising:

• a memory cell array including a plurality memory cells arrayed in first and second directions;
• a plurality of first lines for connecting said memory cells in the first direction;
• a plurality of second lines for connecting said memory cells in the second direction;
• and
• a controller for simultaneously applying a first voltage to said plurality of second lines and for simultaneously biasing said plurality of first lines to a second voltage so that threshold voltages (VTM) of memory cells in an over-erased state rise to that of a memory cell in a non-over-erased state, said second voltage being less than a voltage used to read out a first line.

A non-volatile semiconductor memory, comprising:

• a memory cell block;
• a plurality of word lines coupled to corresponding memory cells of said memory cell block;
• a plurality of bit lines coupled to corresponding memory cells of said memory cell block;
• an erasing circuit for erasing all data stored in said memory cell block;
• and
• an over-erasing correction circuit for applying a first voltage to all word lines, and applying a second voltage to all bit lines for flowing a current to an over-erased memory cell of said memory cell block in order to vary a threshold voltage of said over-erased memory cell.

A non-volatile semiconductor memory, comprising:

• a first memory cell block;
• a second memory cell block;
• a plurality of first word lines coupled to corresponding memory cells of said first memory cell block;
• a plurality of second word lines coupled to corresponding memory cells of said second memory cell block;
• a plurality of first bit lines coupled to corresponding memory cells of said first memory cell block;
• a plurality of second bit lines coupled to corresponding memory cells of said second memory cell block;
• an erasing circuit for erasing all data stored in said first memory cell block and said second memory cell block in response to a first period and a second period, respectively;
• and
• an over-erasing correction circuit for applying a first voltage to all first word lines, and applying a second voltage to all first bit lines for flowing a current to a first over-erased memory cell of said first memory cell block in order to vary a threshold voltage of said first over-erased memory cell in a third period, and for applying said first voltage to all second word lines, and applying a second voltage to all second bit lines for flowing a current to a second over-erased memory cell of said second memory cell block in order to vary a threshold voltage of said second over-erased memory cell in a fourth period.