Data read circuit for use in semiconductor storage apparatus of CMOS memory

A data read circuit for use in a semiconductor storage apparatus of a CMOS memory,

• wherein a memory cell array of said semiconductor storage apparatus is divided into a plurality of memory blocks,
• wherein each of said memory blocks comprises a sense amplifier for amplifying a data output signal from a memory cell,
• wherein a read signal from said sense amplifier of said memory block selected by a block select signal obtained by decoding an external address is transmitted via a read data bus to a data output circuit having a data latch circuit,
• said data read circuit comprising:
• a PMOS transistor for being turned on and off in response to a read signal from said sense amplifier in a data reading stage when said sense amplifier is activated, said PMOS transistor disposed on each of said memory blocks, said PMOS transistor having a drain connected to said read data bus and a source connected to a power source,
• wherein a first level signal is outputted to said read data bus by turning on said PMOS transistor when the read signal from said sense amplifier has a first level, while the read signal from said sense amplifier is stopped from being outputted to said read data bus by turning off said PMOS transistor when the read signal from said sense amplifier has a second level;
• and
• a data output control circuit connected between said read data bus and said data output circuit for generating an output enable signal to control said sense amplifier.

A semiconductor storage apparatus of CMOS memory comprising:

• a memory array having a plurality of memory cells, said plurality of memory cells divided into a plurality of memory blocks;
• and
• a data read circuit for use in said semiconductor storage apparatus,
• wherein a memory cell array of said semiconductor storage apparatus is divided into a plurality of memory blocks,
• wherein each of said memory blocks comprises a sense amplifier for amplifying a data output signal from a memory cell,
• wherein a read signal from said sense amplifier of said memory block selected by a block select signal obtained by decoding an external address is transmitted via a read data bus to a data output circuit having a data latch circuit,
• said data read circuit comprising:
• an NMOS transistor for being turned on and off in response to a read signal from said sense amplifier in a data reading stage when said sense amplifier is activated, said NMOS transistor disposed on each of said memory blocks, said NMOS transistor having a drain connected to said read data bus and a grounded source,
• wherein a first level signal is outputted to said read data bus by turning on said NMOS transistor when the read signal from said sense amplifier has a first level, while the read signal from said sense amplifier is stopped from being outputted to said read data bus by turning off said NMOS transistor when the read signal from said sense amplifier has a second level;
• and
• a data output control circuit connected between said read data bus and said data output circuit for generating an output enable signal to control said sense amplifier.

A semiconductor apparatus of a CMOS memory comprising:

• a memory array having a plurality of memory cells, said plurality of memory cells divided into a plurality of memory blocks;
• and
• a data read circuit for use in said semiconductor storage apparatus,
• wherein a memory cell array of said semiconductor storage apparatus is divided into a plurality of memory blocks,
• wherein each of said memory blocks comprises a sense amplifier for amplifying a data output signal from a memory cell,
• wherein a read signal from said sense amplifier of said memory block selected by a block select signal obtained by decoding an external address is transmitted via a read data bus to a data output circuit having a data latch circuit,
• said data read circuit comprising:
• a PMOS transistor for being turned on and off in response to a read signal from said sense amplifier in a data reading stage when said sense amplifier is activated, said PMOS transistor disposed on each of said memory blocks, said PMOS transistor having a drain connected to said read data bus and a source connected to a power source,
• wherein a first level signal is outputted to said read data bus by turning on said PMOS transistor when the read signal from said sense amplifier has a first level, while the read signal from said sense amplifier is stopped from being outputted to said read data bus by turning off said PMOS transistor when the read signal from said sense amplifier has a second level;
• and
• a data output control circuit connected between said read data bus and said data output circuit for generating an output enable signal to control said sense amplifier.