FPGA memory element programmably triggered on both clock edges

A programmable memory element, comprising:

• an input line;
• an output line;
• a clock line;
• a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output;
• a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output;
• programmable means for selecting between said outputs of said first and second latches and placing said selected latch output on said output line.

A programmable memory element, comprising:

• an input line;
• an output line;
• a clock line;
• a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output;
• a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output;
• programmable means for selecting between said outputs of said first and second latches;
• and
• means for placing said selected latch output on said output line.

A programmable memory element, comprising:

• an input line;
• an output line;
• a clock line;
• a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output;
• a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output;
• a programmable multiplexer controlled by said clock line for selecting between said outputs of said first and second latches and placing said selected latch output on said output line.

A programmable memory element, comprising:

• an input line;
• an output line;
• a clock line;
• a first latch for latching data on said input line in response to a rising edge on said clock line, said first latch having an output;
• a second latch for latching data on said input line in response to a falling edge on said clock line, said second latch having an output;
• a programmable multiplexer controlled by said clock line for selecting between said outputs of said first and second latches, said multiplexer having an output;
• a third latch for programmably latching said output of said multiplexer, said third latch having an output which drives said output line;
• and
• means for programmably configuring the memory element as a single-edge flip-flop.