Memory system
AssigneeKabushiki Kaisha Toshiba
InventorsKen Takeuchi, Tomoharu Tanaka
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AssigneeKabushiki Kaisha Toshiba
InventorsKen Takeuchi, Tomoharu Tanaka
Estimating the term…
A memory system according to the present invention includes a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3, for example, 4) data, wherein the memory cell is operated as an n-level data storing memory cell when the number of times of write-erase sequence is smaller than a predetermined number of times, and the memory cell is operated as an m-level (m is an integer smaller than n, for example, 3) data storing memory cell when the number of times of write-erase sequence has exceeded the predetermined number of times. The number of information items (values) which can be stored in one memory cell is decreased with respect to a predetermined number of times of write-erase sequence. Thus, a memory system including a multi-level data storing memory cell and exhibiting improved durability against write-erase sequence operations is provided.
A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), wherein
A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), wherein
A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), said memory system further comprising
A memory system comprising a memory portion including memory cells comprising
A memory system comprising a memory portion including a memory cell for storing p-level data (p is an integer larger than 2), wherein
A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or greater than 3), wherein
A memory system comprising a memory portion including a memory cell for storing n-level data (n is an integer equal to or larger than 3), wherein
A memory system comprising memory cells, each memory cell capable of storing any one of "n" threshold levels, the threshold levels designating respective states corresponding to the storage of "n"-level data, wherein "n" is an integer equal to or larger than 3 and "n" is decreased for said memory cells when the number of times data is written to or erased from said memory cells exceeds a predetermined number.
Dependencies are inferred from the claim text.