DRAM with open digit lines and array edge reference sensing
AssigneeMicron Technology, Inc.
InventorsPaul S. Zagar, Mirmajid Seyyedy
Life of this patent
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Abstract
A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.
Claims15
An integrated memory circuit having a hierarchical open digit line architecture comprising:
- a global digit line;
- a local digit line coupled to the global digit line through a pass transistor, the pass transistor being controlled by a select line;
- a memory cell capacitor having a first plate and a second plate, the first plate being coupled to a reference voltage and the second plate being coupled to the local digit line through an access transistor, the access transistor being controlled by a word line voltage, the word line voltage having an active voltage level and an inactive voltage level;
- and
- a sense amplifier having a first input selectively coupled to the global digit line and having a second input selectively coupled to a reference circuit for modeling electrical characteristics of the global digit line;
- the reference circuit comprises,
- a truncated global digit line,
- a redundant local digit line coupled to the truncated global digit line through a pass transistor,
- redundant memory cells which can be selectively coupled to the redundant local digit line and used to replace a local digit line or memory cell which is defective, and
- compensating capacitors coupled to the truncated global digit line and sized to model parasitic capacitance of a global digit line.
An integrated memory circuit having a hierarchical open digit line architecture comprising:
- a global digit line;
- a local digit line coupled to the global digit line through a pass transistor, the pass transistor being controlled by a select line;
- a memory cell capacitor having a first plate and a second plate, the first plate being coupled to a reference voltage and the second plate being coupled to the local digit line through an access transistor, the access transistor being controlled by a word line voltage, the word line voltage having an active voltage level and an inactive voltage level;
- and
- a sense amplifier having a first input selectively coupled to the global digit line and having a second input selectively coupled to a reference circuit for modeling electrical characteristics of the global digit line;
- the reference circuit comprises,
- a truncated global digit line,
- compensating capacitors coupled to the truncated global digit line and sized to model parasitic capacitance of a global digit line, and
- a transistor circuit sized to model local digit line pass transistors.
An integrated memory circuit having an open digit line architecture comprising:
- an array of memory cells;
- addressing circuitry for receiving an address of the memory cells;
- and
- control circuitry for controlling read and write operations of the memory device;
- the array of memory cells comprising:
- a memory cell capacitor having a first plate and a second plate, the first plate being coupled to a reference voltage and the second plate being coupled to a digit line through an access transistor, the access transistor being controlled by a word line voltage, the word line voltage having an active voltage level and an inactive voltage level;
- means for modeling electrical characteristics of a digit line;
- and
- a sense amplifier having a first input selectively coupled to the digit line and having a second input selectively coupled to the means for modeling electrical characteristics of the digit line.
A method of reading data stored in a memory device having hierarchical open digit line architecture, the method comprising the steps of:
- equilibrating a global digit line and a reference global digit line to a predetermined voltage, the reference global digit line is coupled to a reference circuit for modeling electrical characteristics of the global digit line;
- activating a first access transistor to access a memory cell;
- charge sharing a charge stored on the memory cell with a local digit line;
- selectively activating a second access transistor coupled to both the global digit line and the local digit line;
- charge sharing a charge of the local digit line with the global digit line;
- amplifying a voltage differential between the global digit line and a reference global digit line to reflect the data stored on the memory cell.
Dependencies are inferred from the claim text.