Executing computer instrucrions by circuits having different latencies

A method to execute computer instructions, the method comprising:

• receiving computer instructions on an input of a computer instruction execution unit;
• if an instruction I1 received on the input belongs to a first category of instructions, and if no instruction was received on the input for at least a predetermined number of clock cycles before the instruction I1, then executing the instruction I1 by a first circuit of the computer unit;
• if the instruction I1 belongs to a second category of instructions, then executing the instructing I1 by a second circuit of the computer unit, wherein the first and second circuits share circuitry, wherein the second circuit comprises a plurality of pipeline stages such that while one of the stages executes one instruction another one of the stages is available to execute another instruction, and wherein execution by the second circuit takes more clock cycles than execution by the first circuit;
• if the instruction I1 belongs to the first category and is received on the input within a predetermined number of clock cycles after an instruction of the second category, then executing the instruction I1 by the second circuit.

A method for providing a computer instruction execution unit, the method comprising:

• providing a first execution path for executing computer instructions;
• and
• providing a second execution path for executing computer instructions, the second path sharing circuitry with the first path, the second path being pipelined, the second path having a higher instruction execution latency than the first path;
• wherein the circuitry shared by the first and second paths comprises a control circuit for causing the instruction execution unit to select either the first or the second path to provide an instruction result, so that:
• the result of a first category instruction received by the execution unit after at least a predetermined number of clock cycles within which no instruction has been received is provided by the first execution path;
• the result of a second category instruction is provided by the second execution path;
• and
• the result of a first category instruction received by the execution unit within a predetermined number of clock cycles of receipt of a second category instruction is provided by the second execution path.

A computer instruction execution unit comprising:

• a first circuit for performing at least a portion of work needed to execute an instruction;
• and
• a second circuit for receiving an output of the first circuit and providing a result of an instruction;
• wherein the instruction execution unit is pipelined so that while the second circuit executes one instruction the first circuit is available to execute another instruction;
• and
• wherein the second circuit comprises a first path operable to execute instructions of a first category but not a second category and a second path operable to execute instructions of the first and second categories, the second path having a greater latency than the first path.

A method to execute computer instructions, the method comprising:

• a first circuit performing at least a portion of work needed to execute an instruction;
• and
• a second circuit receiving an output of the first circuit and providing a result of an instruction;
• wherein while the second circuit executes one instruction the first circuit is available to execute another instruction;
• and
• wherein the second circuit comprises a first path operable to execute instructions of a first category but not a second category and a second path operable to execute instructions of the first and second categories, the second path having a greater latency than the first path.