Shift circuit and system having the same
AssigneeKabushiki Kaisha Toshiba
InventorsHiroki Fujimura, Takashi Miyamora
Life of this patent
Estimating the term…
Abstract
A shift circuit consists of a sequence of a first stage shifter for receiving 32-bit input data, a second stage shifter, and a third stage shifter. The first stage shifter shifts the input data in a higher or lower direction by any one of 0 to 7 bits and provides the second stage shifter with a shifted 32-bit result. Each of the second and third stage shifters receives a shifted 32-bit result from the preceding stage shifter and shifts each byte of the shifted result independently in the higher or lower direction by 8 or 16 bits. The second and third stage shifters consist each of selectors that receive control signals, respectively, to realize various shifting operations on the input data, thereby providing a variety of data operations.
Claims20
A shift circuit comprising a sequence of "n-2" shifters, wherein:
- a first stage shifter receives 2.sup.n -bit input data, shifts the input data in a higher or lower direction by any one of 0 to 7 bits, and provides a second stage shifter with a shifted result;
- and
- any one of the second to "m"th stage shifters receives a shifted 2.sup.n -bit result from preceding stage shifter and independently shifts each byte of the same in the higher or lower direction by 2.sup.(m+1) bits, where n.gtoreq.5 and 2.ltoreq.m.ltoreq.n-2.
A shift circuit comprising a sequence of first, second, and third stage shifters, wherein:
- the first stage shifter receives 16-bit input data, shifts the input data in a higher or lower direction by any one of 0 to 3 bits, and provides the second stage shifter with a shifted result;
- the second stage shifter receives the shifted result from the first stage shifter and independently shifts each 4 bits of the shifted result in the higher or lower direction by 4 bits;
- and
- the third stage shifter receives the shifted result from the second stage shifter and independently shifts each 4 bits of the shifted result in the higher or lower direction by 8 bits.
A system having a shift circuit comprising a sequence of "n-2" shifters, wherein:
- a first stage shifter receives 2.sup.n -bit input data, shifts the input data in a higher or lower direction by any one of 0 to 7 bits, and provides a second stage shifter with a shifted result;
- and
- each of the second to "m"th stage shifters consists of selectors each of which is to select a byte and receives its own shift left and shift amount signals, and each of the second to "m"th stage shifters receives a shifted 2.sup.n -bit result from the preceding stage shifter and shifts each byte thereof independently in the higher or lower direction by 2.sup.(m+1) bits, where n.gtoreq.5 and 2.ltoreq.m.ltoreq.n-2.
A system comprising:
- (a) an execution unit including a shift circuit comprising a sequence of "n-2" shifters, wherein:
- a first stage shifter shifts input data in a higher or lower direction by any one of 0 to 7 bits and provides a second stage shifter with a shifted result;
- and
- each of the second to "m"th stage shifters consists of selectors each for selecting a byte, receives a shifted 2.sup.n -bit result from preceding stage shifter, and shifts each byte thereof independently in the higher or lower direction by 2.sup.(m+1) bits;
- (b) an instruction decoder for providing the selectors and the first stage shifter with independent shift left and shift amount signals;
- and
- (c) a register for supplying 2.sup.n -bit input data to the first stage shifter and receiving the output of the "n-2"th stage shifter, where n.gtoreq.5 and 2.ltoreq.m.ltoreq.n-2.
A system comprising:
- (a) an execution unit including a shift circuit comprising a sequence of first, second, and third stage shifters, wherein:
- the first stage shifter shifts input data in a higher or lower direction by any one of 0 to 3 bits and provides the second stage shifter with a shifted result;
- the second stage shifter consists of selectors each for selecting 4 bits, receives the shifted result from the first stage shifter, and shifts each 4 bits thereof independently in the higher or lower direction by 4 bits;
- and
- the third stage shifter consists of selectors each for selecting 4 bits, receives the shifted result from the second stage shifter, and shifts each 4 bits thereof independently in the higher or lower direction by 8 bits;
- (b) an instruction decoder for providing the selectors and first stage shifter with independent shift left and shift amount signals;
- and
- (c) a register for providing the first stage shifter with 16-bit input data and receiving the output of the third stage shifter.
Dependencies are inferred from the claim text.