Arithmetic shifter that performs multiply/divide by two to the nth power for positive and negative N

A method of operating a circuit to multiply or divide an operand by 2.sup.N, where N is an integer represented in 2's complement form, and an absolute value of N is within a maximum shift count of a first arithmetic left/right shifter, the method comprising the steps of:

• selecting one of multiply and divide;
• left-shifting the operand by the absolute value of N bit positions (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative;
• and
• right-shifting the operand by the absolute value of N bit positions (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive.

A method of operating a circuit to multiply or divide an m-bit operand by 2.sup.N, where N is an integer represented in 2's complement form, the method comprising the steps of:

• selecting one of multiply and divide;
• providing a shift count signal as low-order bits of N when N is positive and as low-order bits of a bit-complement of N when N is negative;
• providing a control signal with a first logical value (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative, and with a second logical value (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive;
• coupling the shift count signal to a shift count input of a first arithmetic left/right shifter;
• coupling the control signal to a shift direction input of the first arithmetic left/right shifter;
• coupling the operand to an operand input of the first arithmetic left/right shifter;
• coupling a first arithmetic shifter output of the first arithmetic left/right shifter to an operand input of a second arithmetic left/right shifter;
• left-shifting the operand by N bit positions in the first arithmetic left/right shifter and not shifting the first arithmetic shifter output in the second arithmetic left/right shifter when multiply is selected and N is positive and within a maximum shift count;
• right-shifting the operand by an absolute value of N minus one bit positions in the first arithmetic left/right shifter and right-shifting the first arithmetic shifter output by one bit position in the second arithmetic left/right shifter when multiply is selected and N is negative and the absolute value of N is within the maximum shift count;
• right-shifting the operand by N bit positions in the first arithmetic left/right shifter and not shifting the first arithmetic shifter output in the second arithmetic left/right shifter when divide is selected and N is positive and within the maximum shift count;
• and
• left-shifting the operand by the absolute value of N minus one bit positions in the first arithmetic left/right shifter and left-shifting the first arithmetic shifter output in the second arithmetic left/right shifter by one bit position when divide is selected and N is negative and the absolute value of N is within the maximum shift count.

An apparatus for multiplying or dividing an operand by 2.sup.N, where N is an integer represented in 2's complement form, and an absolute value of N is within a maximum shift count of a first arithmetic left/right shifter, comprising:

• a logic circuit, including the first arithmetic left/right shifter, that:
• left-shifts the operand by the absolute value of N bit positions (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative;
• and
• right-shifts the operand by the absolute value of N bit positions (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive.

An apparatus for multiplying or dividing an m-bit operand by 2.sup.N, where N is an integer represented in 2's complement form, comprising:

• a shift count generator that provides a shift count signal as low-order bits of N when N is positive and as low-order bits of a bit-complement of N when N is negative;
• a control circuit that responds to a sign bit of N and a function signal, indicative of whether multiply or divide is selected, and provides a control signal with a first logical value (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative, and with a second logical value (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive;
• a first arithmetic left/right shifter that responds to the shift count signal at a shift count input, the control signal at a shift direction input, the operand at an operand input, and provides a first arithmetic shifter output;
• and
• a second arithmetic left/right shifter that responds to a sign bit of N at a shift count input, the function signal at a shift direction input, the first arithmetic shifter output at an operand input, and provides a second arithmetic shifter output.

An apparatus for multiplying or dividing an operand by 2.sup.N, where N is an integer represented in 2's complement form, comprising:

• shift count means for providing a shift count signal as low-order bits of N when N is positive and as low-order bits of a bit-complement of N when N is negative;
• control means that responds to a sign bit of N and a function signal, indicative of whether multiply or divide is selected, for providing a control signal with a first logical value (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative, and with a second logical value (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive;
• first arithmetic left/right shifter means that responds to the shift count signal at a shift count input, the control signal at a shift direction input, and the operand at an operand input, for providing a first arithmetic shifter output;
• and
• second arithmetic left/right shifter means that responds to the sign bit of N at a shift count input, the function signal at a shift direction input, and the first arithmetic shifter output at an operand input, for providing a second arithmetic shifter output.

An apparatus for multiplying or dividing an operand by 2.sup.N, where N is an integer represented in 2's complement form, and an absolute value of N is within a maximum shift count of a left/right shifter, comprising:

• a logic circuit, including the left/right shifter, that:
• left-shifts the operand by the absolute value of N bit positions in a single instruction cycle when N is within the maximum shift count and (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative;
• and
• right-shifts the operand by the absolute value of N bit positions in a single instruction cycle when N is within the maximum shift count and (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive.

An apparatus for multiplying or dividing an m-bit operand by 2.sup.N, where N is an integer represented in 2's complement form, and an absolute value of N is within a maximum shift count of an m-place arithmetic left/right shifter, comprising:

• a logic circuit, including a 2:1 multiplexer and the left/right shifter, that:
• left-shifts the operand by the absolute value of N bit positions in a single instruction cycle when N is within the maximum shift count and (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative;
• right-shifts the operand by the absolute value of N bit positions in a single instruction cycle when N is within the maximum shift count and (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive;
• generates an overflow signal in a single instruction cycle when N exceeds the maximum shift count and (i) when multiply is selected and N is positive, and (ii) when divide is selected and N is negative;
• and
• generates an underflow signal in a single instruction cycle when N exceeds the maximum shift count and (i) when multiply is selected and N is negative, and (ii) when divide is selected and N is positive;
• wherein mantissa bits of N are directly connected to a first operand input of the multiplexer, the operand is directly connected to an operand input of the left/right shifter, a sign bit of N controls a select input of the multiplexer, and an output of the multiplexer controls a shift count input of the left/right shifter.