Bidirectional shifter circuit

A bidirectional shifter circuit for shifting an inputted data word having n bits a chosen number of bit positions COUNT in either a first or second chosen direction comprising:

• a first bit-reversing circuit for, in response to choosing said first direction, outputting said inputted data word with the bits of said data word in order, and, in response to choosing said second direction, outputting said data word with said bits in reverse order,
• a single-direction shifter circuit connected to said first bit-reversing circuit for shifting said bits of said outputted data word said COUNT bit positions in said first direction, and
• a second bit-reversing circuit connected to said shifter circuit for, in response to choosing said first direction, outputting said data word received from said single-direction shifter circuit with said bits of said data word in the same order as received from said single-direction shifter circuit, and, in response to choosing said second direction, outputting said data word with said bits in reverse order,
• wherein said single-direction shifter circuit comprises:
• a first multiplexer stage for shifting said data word k.multidot.q bit positions, where q is an integer>1 and where k=COUNT div q, where div indicates the nearest integer less than or equal to the quotient of n divided by q, said first multiplexer stage receiving only the log.sub.2 (n/q) most significant bits of COUNT as selection control inputs, and
• a second multiplexer stage for further shifting said shifted data word outputted from said first multiplexer stage 0 to q-1 bit positions, said second multiplexer stage receiving only the log.sub.2 q least significant bits of COUNT as selection control inputs,
• wherein said first and second multiplexer stages are comprised of multiplexer substages, each said multiplexer substage comprising a plurality of NMOS and PMOS paired pass transistors, including one pair of pass transistors for each bit inputted to said multiplexer substage, wherein said sources of each transistor of each pair are connected to a signal line receiving a corresponding inputted bit of said multiplexer substage, wherein for each pair of pass transistors corresponding to an odd bit positioned inputted bit, said NMOS transistor receives at its gate a complement of said respective selection control signal and said PMOS transistor receives at its gate said selection control signal, and, wherein for each pair of pass transistors corresponding to an even positioned inputted bit, said NMOS transistor receives at its gate said respective selection control signal and said PMOS transistor receives at its gate said complement of said selection control signal.