HDTV compatible vertical sync separator
AssigneeZenith Electronics Corporation
InventorMichael G. White
Life of this patent
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Abstract
A vertical sync separator circuit that operates with signals that have different arrangements of horizontal equalizing pulses in the vertical interval. The composite signal is integrated and used to operate a Schmidt trigger/inverter that feeds the data input of a D flip/flop. The flip/flop is clocked by the horizontal equalizing pulse that occurs after the beginning of the vertical pulse. In an arrangement that operates without equalizing pulses, a second trigger circuit is operates from a less than one-half line delay and supplies the reset input of the flip/flop. The arrangement provides consistent development of the vertical sync output pulse.
Claims4
A method of processing a video signal comprising:
- integrating a separated composite sync pulse, in a low pass filter that imparts a delay of less than one-half horizontal line at 33 KHz, to remove horizontal rate components;
- supplying the integrated composite sync signal to a flip/flop via a trigger circuit;
- operating the flip/flop with a timing signal derived from the video signal to generate a fixed level vertical sync output;
- and
- applying the timing signal to the clock input of the flip/flop, the timing signal comprising a composite sync pulse in the video signal that occurs after operation of the trigger circuit.
Apparatus for processing a video signal that includes a composite sync pulse comprising:
- means for integrating said composite sync pulse, said means including a low pass filter that imparts a delay of less than one-half horizontal line at 33 KH;
- means, coupled to said integrating means, for developing a fixed signal level;
- a flip/flop having data, clock and reset inputs;
- means for supplying said fixed signal level to said data input;
- means for deriving a timing signal from said video signal, said timing signal comprising a composite sync pulse in said video signal that occurs after development of said fixed signal level;
- and
- means for applying said timing signal to said clock input of said flip/flop to generate a fixed level vertical sync output.
Dependencies are inferred from the claim text.