Flicker elimination system

A flicker-elimination system for compensating for accumulated phase-and-gain errors incurred during transmission of a video signal over a communications channel and resulting in a distorted video signal, and for eliminating flicker, half-line flicker, edge flicker, dot crawl error, and cross modulation error in an interlaced video image, comprising:

• an initial-video processor having a video input and a video output, said initial-video processor including,
• a high-pass filter and inverting amplifier, coupled to said input, for filtering and inverting the distorted video signal received at the input as an inverted-filtered video signal;
• a postcorrection phase-and-gain restorer, coupled to said high-pass filter and inverting amplifier, for restoring a signal level of the inverted-filtered video signal as a restored inverted-filtered video signal;
• a wideband-video delay line, coupled to said input, for delaying the distorted video signal as a delayed video signal;
• a precorrection phase-and-gain restorer, coupled to said wideband-video delay line, for restoring the delayed video signal as a restored-delayed video signal;
• and
• a combining network, coupled to said video output, to said postcorrection phase-and-gain restorer, and to said precorrection phase-and-gain restorer, for combining the restored inverted-filtered video signal and the restored-delayed video signal, and outputting a composite video signal to said video output;
• and
• a digital processor, coupled to the output of the initial-video processor, said digital processor including,
• an input-video processor, coupled to the output of said initial-video processor, for converting the composite video signal into digital-component signal information;
• a feature-video processor, coupled to said input-video processor, for processing the digital-component signal information to generate processed component video information;
• a frame buffer, coupled to said feature-video processor, for re-establishing broadcast timing standards in the processed component video information to generate time-base corrected digital information;
• an RGB-output processor, coupled to said frame buffer, for decoding the time-base corrected digital information to generate analog RGB outputs for direct output and to generate digital RGB outputs;
• an output-video processor, coupled to said RGB-output processor, for reconstructing the digital RGB outputs into an analog-composite video-signal format and an analog-component video-signal format;
• a control processor, coupled to said input-video processor, said feature-video processor, and said output-video processor, for initializing and updating a set of parameters used to process the composite video signal, and for generating a vertical-scan synchronization pulse for a vertical-scan rate and a horizontal-scan synchronization pulse for a horizontal-scan rate;
• and
• a vertical-and-horizontal synchronized-clock doubler, coupled to said control processor, to said frame buffer and to said output-video processor, said vertical-and-horizontal synchronized-clock doubler for harmonically doubling the vertical-scan synchronization pulse received from the control processor and for harmonically doubling the horizorntal-scan synchronization pulse received from the control processor to generate harmonically doubled synchronization pulses, and for inputting the harmonically doubled synchronization pulses to said frame buffer and to said output-video processor;
• said frame buffer, responsive to the harmonically doubled synchronization pulses, reading the time-base corrected digital information at a harmonically doubled vertical-scan rate and at a harmonically doubled horizontal-scan rate to produce a visually enhanced interlaced video display image.

A method of eliminating flicker in an interlaced video display image, comprising the steps of:

• processing an input video signal as processed component video information;
• writing the processed component video information to a video memory at a horizontal-scan rate and a vertical-scan rate;
• generating, based on the input video signal, a vertical-scan synchronization pulse and a horizontal-scan synchronization pulse;
• harmonically doubling the vertical-scan synchronization pulse and the horizontal-scan synchronization pulse as harmonically doubled synchronization pulses;
• reading the processed component video information from the video memory, responsive to the harmonically doubled synchronization pulses, at a harmonically doubled horizontal-scan rate and a harmonically doubled vertical-scan rate reading in an interlaced format, with each frame being contiguously read twice in a proper odd-even order as when normally read at the horizontal-scan rate and the vertical-scan rate, to generate four fields of video information per frame which, because of the proper odd-even order, may be interlaced;
• and
• interlacing the four fields of video information per frame to generate a video display image having enhanced resolution, color saturation, brightness and contrast ratio, the video display image, responsive to the doubled synchronization pulses being derived from the input video signal, being harmonic to any one of NTSC, PAL and SECAM broadcast standards.