US 5,844,605 AGranted

Analog processing element (APE) and related devices

AssigneeIntegrated Data System, Inc.

InventorVladimir Gorelik

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Abstract

Disclosed is an analog processing element (APE) for the analog processing of charge packets present in an analog signal. The APE utilizes CCD-based elements in a semi-conductor device to move and process charge packets present in an analog signal. In one embodiment, the APE provides analog processing on dimensional signals such as audio or video signals. When the APE is embodied in a semi-conductor device, it may be provided as a chip for analog pre-processing of video or audio signals such as for compression of the signal prior to digitization and use by digital processing devices. In a particular embodiment, an array of APE's, along with related circuitry provides for a pipelined Pattern Recognition Processor (PRP). The PRP may perform analog video compression at rates substantially exceeding compression rates available with current digital processing technology.

Claims23

Dependent claims

An apparatus for processing video information stored in a first and second video frame, wherein each video frame includes a two dimensional array of analog pixel elements and each pixel element is represented by a charge packet carried on a charge-coupled device (CCD) element, the apparatus comprising:

a matrix of CCD intersection points formed from two orthogonally-disposed arrays of CCD lines;
transport means for controllably moving a matrix of analog charge packets from the second video frame among the intersection points;
a plurality of pixel block units defined within the matrix of intersection points, each pixel block unit further comprising:
a two dimensional array of analog processing elements (APEs) integrally disposed with the CCD intersection points, each APE including:
a first CCD element for storing the magnitude of charge of a pixel element of the second video frame, the first CCD element being located at an intersection point;
a second CCD element for storing the magnitude of charge of a pixel element of the first video frame and previously stored at the first CCD element;
means for moving a packet of charge from the first CCD element to the second CCD element;
a subtractor operative to generate a difference output that is proportional to the magnitude of the difference in charge between the charges stored on the first and second CCD elements;
adding means for adding the difference output of the subtractor with an output of an adding means of an adjacently disposed analog processing element;
and
control means for controlling the movement of charge packets among the plurality of analog processing elements, the subtractor, and the adding means so that the adding and subtracting operations among all the analog processing elements occurs substantially simultaneously;
processing control means for controlling the transport of the matrix of charge packets of the second video frame within the intersection points in accordance with a predetermined processing pattern;
master summation means responsive to the subtractors of the plurality of APEs for generating a single signal that is representative of the summation of the difference outputs for the plurality of subtractors;
storage means for storing the minimum value of the master summation means over a plurality of summation calculations, wherein the plurality of summation calculations include calculations made as the matrix of charge packets of the second video frame is transported among the intersection points;
and
position indication means responsive to the storage means for storing position information;
whereby video information pertaining to the second frame of video information may be stored and communicated by the values stored in the storage means and the position indication means.

14 more elements

An apparatus for pipelining successive frames of video information represented by a two-dimensional array of pixels, wherein each pixel comprises a packet of charge, the apparatus comprising a two dimensional array of analog processing elements each having an intersection point and a processing element that carry corresponding charge packets from successive video frames, the analog processing elements are disposed in a two-dimensional array wherein each intersection point is in communication with four intersection points of adjacent analog processing elements, the apparatus comprising:

a line buffer having a plurality of CCD elements for storing a plurality of charge packets, the line buffer in communication with a first row of intersection points;
receiving means for receiving a stream of charge packets representative of a row of pixels of the two dimensional array of pixels and shifting the received charge packets into the line buffer;
a buffer element associated with each analog processing element, the buffer element in communication with the intersection point associated with the corresponding analog processing element, for storing a packet of charge;
a stack element in communication with an intersection point associated with the corresponding analog processing element, for storing a packet of charge the stack element and buffer element being in communication with a common gate;
and
charge moving means for controllably moving charge packets among the intersection points, buffer elements, and stack elements, in response to a complete row of charge packets being received and shifted into the line buffer.

3 more elements

In an apparatus for processing successive frames of video information represented by a two-dimensional array of pixels, wherein each pixel comprises a packet of charge, the apparatus comprising a two dimensional array of analog processing elements each having a buffer element CCD, a stack element CCD, and an intersection point disposed for intercommunication of charge packets, wherein each intersection point is further disposed in communication with four intersection points of adjacent analog processing elements, a method of pipelining the processing of a fist frame of video information with the receipt of a second, successive frame of video information comprising the steps of:

(a) receiving a stream of charge packets representative of a row of pixels of the two dimensional array of pixels;
(b) shifting the received charge packets into a line buffer;
(c) entering a shift-state after an entire row of pixel information has been shifted into the line buffer;
(d) shifting the charge packets in the intersection points into the associated buffer elements;
(e) shifting the charge packets in the stack elements into the associated intersection points;
(f) shifting the charge packets in the intersection points to the adjacent row of intersection points, and shifting the charge packets in the line buffer into a first row of intersection points;
(g) shifting the charge packets in the intersection points into the associated stack elements;
and
(h) shifting the charge packets in the buffer element into the associated intersection points.

6 more elements

a line buffer having a plurality of CCD elements for storing a plurality of charge packets, the line buffer in communication with a first row of intersection points;
receiving means for receiving a stream of charge packets representative of a row of pixels of the two dimensional array of pixels and shifting the received charge packets into the line buffer;
a buffer element associated with each analog processing element, the buffer element in communication with the intersection point associated with the corresponding analog processing element, for storing a packet of charge;
a stack element in communication with an intersection point associated with the corresponding analog processing element, for storing a packet of charge;
and
charge moving means for controllably moving charge packets among the intersection points, buffer elements, and stack elements, in response to a complete row of charge packets being received and shifted into the line buffer.

3 more elements

Dependencies are inferred from the claim text.