Digital to analog converter and bias circuit therefor

A converter comprising:

• an array having a plurality of current cells;
• at least one decoder for decoding an applied digital data;
• a bias circuit for biasing said plurality of current cells;
• a latch circuit coupled to said at least one decoder and said array;
• and
• a clock generator coupled to said latch circuit such that decoded signals from said at least one decoder are applied to said array in synchronization, wherein
• each current cell of said array has a prescribed layout and said array has a group of current cells where each current cell has a different layout orientation of an adjacent current cell in the group.

A converter comprising:

• an array having a plurality of current cells;
• at least one decoder for decoding an applied digital data;
• and
• a bias circuit for biasing said plurality of current cells, wherein each current cell includes
• a current source coupled between a source potential and a node;
• and
• a switching circuit coupled to the node and including
• a) serially connected transistors coupled between the node and a ground potential,
• b) a first transistor coupled in parallel with said serially connected transistors, and
• c) a second transistor coupled between the node and an output line of the converter.