Oscillator device generating signals of different cycles

An oscillating device comprising:

• a first ring oscillator having at least three inverters connected in series, an input terminal of the first of the inverters being connected with an output terminal of the last of the inverters, and producing a first-cycle output signal of the last inverter to one input terminal of output means;
• a second ring oscillator having at least three delay devices connected in series, wherein a power supply of each delay device is connected with the output terminal of each of the first ring oscillator's corresponding inverters, and an output terminal of the last of the delay devices connected with an input terminal of the first of the delay devices, thus producing a signal of the second cycle to another input terminal of said output means;
• and
• said output means receiving the first-cycle output signal of the first ring oscillator and the second-cycle output signal of the second ring oscillator, thus producing an output signal of the first cycle when a mode signal attains a high level, and producing an output signal of the second cycle when the mode signal attains a low level.

An oscillating device comprising:

• first short-cycle output signal generating means including at least three MOS transistors, said MOS transistors each having a gate terminal receiving an inverted output of a mode signal when the mode signal attains a high level, and producing a short-cycle first output signal;
• one first long-cycle output signal generating means including at least three MOS transistors, said MOS transistors each having a gate terminal receiving an output signal from a node of first transmission means and second output signal generating means or an output signal from a node of the second output signal generating means and second stage-front transmission means, and producing a long-cycle first output signal when the mode signal attains a high level;
• the first transmission means connected between the first long-cycle output signal generating means and the second output signal generating means, and transmitting a power supply voltage sent by the first short-cycle output signal generating means and the first long-cycle output signal generating means, to the node of the second output signal generating means;
• the second output signal generating means having at least three delay means connected between the first transmission means and second stage-front transmission means, and producing a second output signal;
• the second stage-front transmission means connected between the second output signal generating means and the first long-cycle output signal generating means, and transmitting a ground voltage, transmitted by the first short-cycle output signal generating means or the first long-cycle output signal generating means, to the node of the second output signal generating means;
• the other first long-cycle output signal generating means having at least three MOS transistors connected between the second transmission means and first short-cycle output signal generating means, and producing a first signal of long cycle when the mode signal attains a low level;
• and
• the first short-cycle output signal generating means having at least three odd MOS transistors each having a gate terminal receiving the mode signal when the mode signal is at high level, and producing a first signal of short cycle.