Oscillator based tamperproof precision timing circuit

An oscillator having an oscillating voltage and a reference voltage, comprising:

• a first circuit coupled to receive said oscillating voltage, said reference voltage, and a first signal, said first circuit providing said oscillating voltage on a first output and said reference voltage on a second output if said first signal is in a first state and providing said reference voltage on said first output and said oscillating voltage on said second output if said first signal is in a second state;
• a comparator having a first input coupled to said first output, a second input coupled to said second output, and a third output having a third signal;
• and
• a second circuit coupled to said third output for providing said third signal if said first signal is in said first state and providing a complement of said third signal if said first signal is in said second state.

A speed governor comprising:

• an oscillator comprising:
• a voltage reference configured to provide a substantially-constant first voltage;
• a first capacitor;
• a first circuit coupled to receive said substantially-constant first voltage and configured to charge said first capacitor to a second voltage;
• a second circuit configured to produce a substantially-constant third voltage;
• a comparator coupled to receive said second voltage and said substantially-constant third voltage and configured to produce a first signal having a first plurality of pulses depending on a first comparison result;
• and
• a third circuit configured to produce a second signal having a second plurality of pulses, the second signal generated in response to the first signal, the first capacitor coupled to be discharged in response to the second signal;
• a counter coupled to receive said first signal and said second signal, said counter configured to count said first plurality of pulses to produce a counter value, said counter value being reset by each of said second plurality of pulses;
• and
• a fourth circuit coupled to said counter and configured to generate a third signal indicating a second comparison result of said counter value to a predetermined first value.

An integrated circuit comprising:

• a speed governor comprising:
• an oscillator comprising:
• a voltage reference configured to provide a substantially-constant first voltage;
• a first capacitor;
• a first circuit coupled to receive said substantially-constant first voltage and configured to charge said first capacitor to a second voltage;
• and
• a second circuit configured to produce a substantially-constant third voltage;
• a comparator coupled to receive said second voltage and said third substantially-constant voltage and configured to produce a first signal having a first plurality of pulses depending on the comparison result of said second voltage and said third substantially-constant voltage;
• and
• a third circuit configured to produce a second signal having a second plurality of pulses, the second signal generated in response to the first signal, the first capacitor coupled to be discharged in response to the second signal;
• a counter coupled to receive said first signal and said second signal, said counter configured to count said first plurality of pulses to produce a counter value, said counter value being reset by each of said second plurality of pulses;
• and
• a fourth circuit coupled to said counter and configured to generate a third signal indicating the comparison result of said counter value to a predetermined first value;
• and
• a functional block;
• a disable circuit configured configured to selectively disable said functional block in response to said third signal.

In a speed governor, a method comprising the steps of:

• generating a first signal having a first state and a second state;
• receiving a clock signal having a plurality of pulses;
• switching a pair of inputs of an operational amplifier in response to each transition between said first state and said second state;
• inverting an output signal of the operational amplifier in response to said first signal;
• and
• counting said plurality of pulses during a period in which said first signal has been equally in said first state and said second state.