High votage latch using CMOS transistors and method therefor

A method of providing a high voltage latch for operation at relatively high power supply voltages comprising the steps of:

• providing high voltage rail means for supplying an upper voltage level;
• providing low voltage rail means for supplying a lower voltage level wherein said lower voltage level is approximately ground when said high voltage latch operates in a low voltage mode and said lower voltage level is greater than ground and less than said upper voltage level when said high voltage latch operates in a high voltage mode;
• providing latch means coupled to said high voltage rail means and to said lower voltage rail means for generating an output signal and a complementary output signal wherein said output signal and said complementary output signal switch with respect to an input signal when said high voltage rail means and said low voltage rail means operate in said low voltage mode and said output signal and said complementary output signal are latched in a state that said output signal and said complementary output signal are currently at when said high voltage rail means and said low voltage rail means changes state from said low voltage mode to said high voltage mode;
• providing input means coupled to said latch means for sending said input signal and a complementary input signal to said latch means;
• and
• providing output terminal means coupled to said latch means for outputting said output signal and said complementary output signal.

A high voltage latch for operation at relatively high power supply voltages-comprising, in combination:

• high voltage rail means for supplying an upper voltage level;
• low voltage rail means for supplying a lower voltage level wherein said lower voltage level is approximately ground when said high voltage latch operates in a low voltage mode and said lower voltage level is greater than ground and less than said upper voltage level when said high voltage latch operates in a high voltage mode;
• latch means coupled to said high voltage rail means and to said low voltage rail means for generating an output signal and a complementary output signal wherein said output signal and said complementary output signal switch with respect to an input signal when said high voltage rail means and said low voltage rail means operate in said low voltage mode and said output signal and said complementary output signal are latched in a state that said output signal and said complementary output signal are currently at when said high voltage rail means and said low voltage rail means changes state from said low voltage mode to said high voltage mode;
• an input means coupled to said latch means for sending said input signal and a complementary input signal to said latch means, said input means comprising:
• an input terminal means coupled to said latch means for receiving said input signal and for sending said input signal to said latch means;
• and
• an inverter means having an input coupled to said input terminal means and an output coupled to said latch means for generating said complementary input signal and for sending said complementary input signal to said latch means;
• and
• an output terminal means coupled to said latch means for outputting said output signal and said complementary output signal;
• said latch means comprising:
• a first transistor having a gate, drain and source terminal wherein said gate terminal of said first transistor is coupled to said input terminal means, said source terminal of said first transistor is coupled to said low voltage rail means, and said drain terminal of said first transistor is coupled to said output terminal means;
• a second transistor having a gate, drain and source terminal wherein said gate terminal of said second transistor is coupled to said output of said inverter means, said source terminal of said second transistor is coupled to said low voltage rail means, and said drain terminal of said second transistor is coupled to said output terminal means;
• a third transistor having a gate, drain and source terminal wherein said gate terminal of said third transistor is coupled to said drain terminal of said second transistor, said drain terminal of said third transistor is coupled to said high voltage rail means, and said source terminal of said third transistor means is coupled to said output terminal means;
• a fourth transistor having a gates drain and source terminal wherein said gate terminal of said fourth transistor is coupled to said drain terminal of said first transistor, said drain terminal of said fourth transistor is coupled to said high voltage rail means, and said source terminal of said fourth transistor means is coupled to said output terminal means;
• holding means coupled to said output terminal means for holding said output signal and said complementary output signal of said latch means in a present state, said holding means comprising:
• a fifth transistor having a gate, drain and source terminal wherein said gate terminal of said fifth transistor is coupled to said gate terminal of said third transistor, said drain terminal of said fifth transistor is coupled to said gate terminal of said fourth transistor and to said output terminal means, and said source terminal of said fifth transistor is coupled to said low voltage rail means;
• and
• a sixth transistor having a gate, drain and source terminal wherein said gate terminal of said sixth transistor is coupled to said gate terminal of said fourth transistor, said drain terminal of said sixth transistor is coupled to said gate terminal of said third transistor and to said output terminal means, and said source terminal of said sixth transistor is coupled to said low voltage rail means;
• and
• switching means coupled to input means for allowing said output signal and said complementary output signal to switch faster with respect to said input signal when said high voltage rail means and said low voltage rail means operate in said low voltage mode, said switching means comprising:
• a seventh transistor having a gate, drain and source terminal wherein said gate terminal of said seventh transistor is coupled to said input terminal means, said drain terminal of said seventh transistor is coupled to said high voltage rail means, and said source terminal of said seventh transistor is coupled to said gate terminal of said fifth transistor;
• and
• an eighth transistor having a gate, drain and source terminal wherein said gate terminal of said eighth transistor is coupled to said output of said inverter means, said drain terminal of said eighth transistor is coupled to said high voltage rail means, and said source terminal of said eighth transistor is coupled to said gate terminal of said sixth transistor.