Method of recovering a sampling clock in a framed data communications format with reduced phase jitter and wander

A method of sampling framed data in order to recover data therefrom, where periodic data frames have a reference timing mark, comprising the steps of:

• generating a clock signal having a nominal frequency which is an integer multiple of a data rate of said framed data and an integer multiple of a reference timing mark rate;
• generating a multiplicity of phases for said clock signal;
• detecting cycles of said clock signal;
• detecting said reference timing mark;
• sensing a time difference between a time when said reference timing mark is detected and a time when a number of clock cycles equivalent to said integer multiple of said reference timing mark rate is detected;
• continually changing phases of said clock signal at a phase change rate based on a magnitude of said time difference to produce a phase changing clock signal;
• and
• sampling data based on said phase changing clock signal.

Apparatus for sampling framed data in order to recover a data stream therefrom, where periodic data frames have a reference timing mark, comprising:

• a selectable phase clock signal generator for generating a clock signal having a nominal frequency which is an integer multiple of a data rate of said framed data and an integer multiple of a reference timing mark rate, said clock signal having a plurality of phases, said selectable phase clock signal generator outputting a selected phase of said clock signal, for use in sampling framed data;
• a local timer responsive to said output from said selectable phase clock generator for detecting cycles of said selected phase of said clock signal and for generating a local timing mark whenever a pre-set number of clock signal cycles are detected;
• a phase detector for responding to a source of framed data to detect said reference timing mark of said framed data and responsive to said local timing mark output from said local timer, said phase detector for outputting a signal indicating time difference between a time when said reference timing mark signal is detected and a time when said local timing mark is received from said local timer;
• a clock signal controller responsive to output from said phase detector for controlling said selectable phase clock signal generator to select one of said plurality of phases of said clock signal.