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US 5,844,431 AGranted
Low noise low power CMOS correlated double sampler
AssigneeExar Corporation
InventorXiaole Chen
Life of this patent
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Abstract
An improved CMOS CDS circuit which can operate on 2.7 volts, provides increased noise immunity and can handle a 0.8 volts maximum signal input. The present invention provides internal capacitors to isolate the input pads. The present invention also provides switches and capacitors to perform a sample and hold function on every pixel value.
Claims9
A CMOS correlated double sampler circuit, comprising:
- a signal input node;
- a reference input node;
- a first transconductor, having inputs coupled to said signal input node and said reference input node, configured to produce a differential current output from voltages on said nodes;
- a first internal capacitor coupled between said signal input node and a first input of said first transconductor;
- a second internal capacitor coupled between said reference input node and a second input of said first transconductor;
- a second transconductor, coupled to a first output of said first transconductor, configured to convert a current into a voltage;
- a third transconductor, coupled to a second output of said first transconductor, configured to convert a current into a voltage;
- a first sampling switch coupled to the first output of said first transconductor;
- a first sampling capacitor coupled to said first sampling switch;
- second sampling switch coupled to the second output of said first transconductor;
- and
- a second sampling capacitor coupled to said second sampling switch.
9 more elements
A CMOS correlated double sampler circuit, comprising:
- a signal input node;
- a reference input node;
- a first transconductor, having inputs coupled to said signal input node and said reference input node, configured to produce a differential current output from voltages on said nodes, said first transconductor including a high gain transconductor and a low gain transconductor;
- a first internal capacitor coupled between said signal input node and a first input of said first transconductor;
- a second internal capacitor coupled between said reference input node and a second input of said first transconductor;
- a switching circuit configured to connect said nodes to said low gain transconductor in response to a low gain signal, and to connect said nodes to said high gain transconductor in response to a high gain signal;
- a second transconductor, coupled to a first output of said first transconductor, configured to convert a current into a voltage;
- a third transconductor, coupled to a second output of said first transconductor, configured to convert a current into a voltage, said second and third transconductors comprising third and fourth MOS transistors;
- a first sampling switch coupled to said second transconductor;
- a first sampling capacitor coupled to said first sampling switch;
- a second sampling switch coupled to said third transconductor;
- a second sampling capacitor coupled to said second sampling switch;
- a fourth transconductor having first and second inputs coupled to said first and second sampling switches, and configured to provide a differential current output signal, said fourth transconductor comprising first and second MOS transistors;
- said first and third MOS transistors being connected as a first current mirror;
- and
- said second and fourth MOS transistors being connected as a second current mirror.
13 more elements
Dependencies are inferred from the claim text.