Burn-in sensing circuit

A device for increasing a potential difference between a burn-in entry and exit voltages when a signal indicates a burn-in operation of semiconductor device, comprising:

• first and second transistors coupled in series, both gates commonly coupled to a first node receiving the signal, and electrodes commonly connected to a second node;
• and
• a circuitry that adjusts a logic threshold potential level at the second node, wherein said circuitry comprises,
• a first serially coupled pair of transistors coupled between said second node and a third node,
• a second serially coupled pair of transistors coupled between the second node and the third node, and
• a third transistor to coupled to said second node, wherein the circuitry increases a potential difference between a burn-in entry and exit voltages when a signal indicating the burn-in operation is present at the second node.

A circuit for detecting one of a normal and burn-in operations of a semiconductor device, comprising:

• a) a sensor receiving a first signal of first and second levels and outputting to a first node a first prescribed potential when said sensor detects the first level and a second prescribed potential when said sensor detects the second level, wherein said sensor comprises a pair of serially connected transistors in a diode configuration, one of said pair of transistors receiving the first signal and another coupled to said first node, and a bias transistor having a gate receiving a second signal, a drain coupled to said first node, and a source coupled to a second potential;
• and
• b) a signal generator coupled to said first node, said signal generator including
• i) an inverter circuit coupled to said first node and outputting to a second node a first output signal indicative of a normal operation when receiving the first prescribed potential and a second output signal indicative of the burn-in operation when receiving the second prescribed potential, and
• ii) a circuitry that adjusts a logic threshold potential level of said inverter circuit at said second node, wherein said circuitry comprises a first transistor coupled to said second node and a first switch coupled to said first transistor at a third node and said first node.