Driver circuit for use with a sensing amplifier in a memory

A driver circuit for driving a sensed logic voltage sensed by a sensing amplifier of a memory block of a memory onto a data line of the memory in response to first complementary sensing signals, second complementary sensing signals, and memory block control signals, the first and second complementary sensing signals indicating whether sensing or equalization is occuring in the sensing amplifier, the second complementary sensing signals being delayed versions of the first complementary sensing signals, the memory block control signals indicating whether or not a data word is being read from the memory, the driver circuit comprising:

• an input terminal for coupling to the sensing amplifier to receive the sensed logic voltage;
• an output terminal for coupling to the data line;
• a first node, a second node, and a third node;
• an input transfer gate that is coupled between the input terminal and the first node and is responsive to the second complementary sensing signals;
• a first inverter gate that is coupled between the first and second nodes;
• a second inverter gate that is coupled between the second and third nodes;
• an output transfer gate that is coupled between the third node and the output terminal and is responsive to the memory block control signals;
• and
• a latching loop that is coupled between the output terminal and the first node and is responsive to the first complementary sensing signals;
• when the first and second complementary sensing signals indicate that equalization is occuring and the memory block control signals indicate that the data word is being read from the memory block, the input transfer gate de-couples the input terminal and the first node, the latching loop couples the output terminal to the first node and passes a data line logic voltage at the output terminal and on the data line to the first node, the first inverter gate inverts the data line logic voltage at the first node to an inverted logic voltage at the second node, the second inverter gate inverts the inverted logic voltage at the second node back to the data line logic voltage at the third node, the output transfer gate couples the third node and the output terminal and passes the data line logic voltage from the third node to the output terminal to latch the data line logic voltage on the data line without any false transitions or glitches occuring on the data line;
• when the first and second complementary sensing signals indicate that sensing is occuring and the memory block control signals still indicate that the data word is being read from the memory block, the latching loop de-couples the output terminal and the first node, the input transfer gate couples the input terminal and the first node and passes the sensed logic voltage from the input terminal to the first node, the first inverter gate inverts the sensed logic voltage at the first node to an inverted logic voltage at the second node, the second inverter gate inverts the inverted logic voltage at the second node back to the sensed logic voltage, the output transfer gate passes the sensed logic voltage from the third node to the output terminal to drive the sensed logic voltage onto the data line.

A driver circuit for driving a sensed logic voltage sensed by a sensing amplifier of a memory block of a memory onto a data line of the memory in response to first complementary sensing signals, second complementary sensing signals, and memory block control signals, the first and second complementary sensing signals indicating whether sensing or equalization is occurring in the sensing amplifier, the second complementary sensing signals being delayed versions of the first complementary sensing signals, the memory block control signals indicating whether or not a data word is being read from the memory, the driver circuit comprising:

• an input terminal for coupling to the sensing amplifier to receive the sensed logic voltage;
• an output terminal for coupling to the data line;
• a first node, a second node, and a third node;
• an input transfer gate that is coupled between the input terminal and the first node and is responsive to the second complementary sensing signals;
• a first inverter gate that is coupled between the first and second nodes;
• a transfer loop that is coupled in parallel to the first inverter gate between the first and second nodes and is responsive to the first complementary sensing signals and at least one of the second complementary sensing signals;
• a second inverter gate that is coupled between the second and third nodes;
• an output transfer gate that is coupled between the third node and the output terminal and is responsive to the memory block control signals;
• and
• a latching loop that is coupled between the output terminal and the first node and is responsive to the first complementary sensing signals;
• when the first and second complementary sensing signals indicate that equalization is occurring and the memory block control signals indicate that the data word is being read from the memory block, the input transfer gate de-couples the input terminal and the first node, the latching loop couples the output terminal to the first node and passes the data line logic voltage at the output terminal and on the data line to the first node, the transfer loop de-couples the first and second nodes, the first inverter gate inverts a data line logic voltage at the first node to an inverted logic voltage at the second node, the second inverter gate inverts the inverted logic voltage at the second node back to the data line logic voltage at the third node, the output transfer gate couples the third node and the output terminal and passes the data line logic voltage from the third node to the output terminal to latch the data line logic voltage on the data line without any false transitions or glitches occurring on the data line;
• when the first complementary sensing signals indicate that sensing is occurring, the second complementary sensing signals still indicate that equalization is occurring, and the memory block control signals still indicate that the data word is being read from the memory block, the latching loop de-couples the output terminal and the first node, the input transfer gate still de-couples the input terminal and the first node, the transfer loop directly couples the first and second nodes together so that the first inverter gate biases the first node to a bias voltage, and the output transfer gate still couples the third node and the output terminal together;
• when the first and second complementary sensing signals indicate that sensing is occurring and the memory block control signals still indicate that the data word is being read from the memory block, the latching loop still de-couples the output terminal and the first node, the input transfer gate couples the input terminal and the first node together so that the sensed logic voltage is passed from the input terminal to the first node, the transfer loop de-couples the first and second nodes so that a minimal voltage swing from the bias voltage to the passed logic voltage occurs at the first node, the first inverter gate inverts the passed logic voltage at the first node to an inverted logic voltage at the second node, the second inverter gate inverts the inverted logic voltage at the second node back to the sensed logic voltage, the output transfer gate passes the sensed logic voltage from the third node to the output terminal to drive the sensed logic voltage onto the data line.