CMOS tristate output buffer with having overvoltage protection and increased stability against bus voltage variations

An output buffer, said output buffer having an output terminal for coupling to a bus, said output buffer having a first power supply node for coupling to a first power supply voltage, said output buffer also having a second power supply node for coupling to a second power supply voltage lower than said first power supply voltage, said output buffer having a drive mode and a high impedance mode, said output buffer driving said output terminal between substantially said first power supply voltage and said second power supply voltage in said drive mode, said output buffer having a high input impedance at said output terminal in said high impedance mode, said output terminal being driven at a bus voltage in said high impedance state, said bus voltage being capable of exceeding said first voltage, said output buffer comprising:

• a P-channel driver transistor having a source coupled to the first power supply node and a drain coupled to said output terminal, said P-channel driver transistor being in an N-well;
• an N-well bias circuit for biasing said N-well to a voltage sufficient to prevent forward biasing of said drain with respect to said N-well during said high impedance mode, said N-well bias circuit including a latch means, said latch means including a sensing circuit having a first state and a second state, said sensing circuit being coupled to the first power supply node and to the output terminal, said sensing circuit switching to said first state when said bus voltage goes below a lower switchover voltage less than the first power supply voltage, said sensing circuit switching to said second state when said bus voltage goes above an upper switchover voltage higher than the first power supply voltage, said N-well bias circuit further comprising:
• a switch circuit coupled to said N-well, said first power supply node, and said output terminal, said switch circuit for engaging said first power supply node to said N-well responsive to said first state of said sensing circuit, said switch circuit for engaging said output terminal to said N-well responsive to said second state of said sensing circuit;
• and
• means for coupling said latch means to said switch circuit;
• whereby
• said N-well voltage is stabilized against bus voltage variations near said first power supply voltage during said high impedance mode.

A CMOS tristate output buffer having an output terminal for coupling to a bus, a first power supply node for coupling to a first power supply voltage, a reference node for coupling to a reference voltage, said output buffer for driving said output terminal between said first power supply voltage and a reference voltage in a drive mode, said output buffer having a high input impedance at said output terminal in a tristate mode, said output buffer comprising:

• a P-channel driver transistor coupled between the first power supply node and said output terminal, said P-channel driver transistor being in an N-well;
• an N-well bias circuit coupled to said N-well, said first power supply node, and said output terminal for providing an N-well bias voltage to said N-well responsive to a voltage at said output terminal relative to said first power supply voltage, said N-well bias circuit having an input hysteresis characteristic for providing N-well bias circuit stability, said N-well bias circuit comprising:
• a first transistor coupled between said first power supply node and said N-well and having a control node;
• a second transistor coupled between said output terminal and said N-well and having a control node;
• and
• means for controlling said first and second transistors, wherein said first and second switch transistors are controlled responsive to both (a) a present output terminal voltage relative to said first power supply voltage, and (b) at least one past output terminal voltage for providing N-well bias circuit stability.

A CMOS tristate output buffer having an output terminal for coupling to a bus, a first power supply node for coupling to a first power supply voltage, a reference node for coupling to a reference voltage, said output buffer for driving said output terminal between said first power supply voltage and a reference voltage in a drive mode, said output buffer having a high input impedance at said output terminal in a tristate mode, said output buffer comprising:

• a P-channel driver transistor coupled between the first power supply node and said output terminal, said P-channel driver transistor being in an N-well;
• an N-well bias circuit coupled to said N-well, said first power supply node, and said output terminal for providing an N-well bias voltage to said N-well responsive to a voltage at said output terminal relative to said first power supply voltage, said N-well bias circuit comprising a comparator;
• a gate bias circuit for coupling said N-well to a gate of said P-channel driver transistor during said tristate mode;
• a P-channel predriver transistor having a gate, a drain, and a source, said source being coupled to said first power supply node;
• an N-channel predriver transistor having gate coupled to said gate of said P-channel predriver transistor, a drain, and a source coupled to said reference node;
• a resistor coupled between said drain of said N-channel predriver transistor and a gate of said P-channel driver transistor;
• a P-channel switch transistor coupled between said drain of said P-channel driver transistor and said gate of said P-channel driver transistor and having a gate;
• means for driving said gate of said P-channel switch transistor such that said P-channel switch transistor is turned off when a voltage at said output terminal-exceeds said first power supply voltage during tristate mode, said means for driving comprising a sensing circuit having a first state and a second state, said sensing circuit being coupled to the first power supply node and to the output terminal, said sensing circuit switching to said first state when said bus voltage goes below a lower switchover voltage less than the first power supply voltage, said sensing circuit switching to said second state when said bus voltage goes above an upper switchover voltage higher than the first power supply voltage;
• whereby
• reverse currents from said gate of said P-channel driver transistor to said first power supply node through said P-channel predriver transistor during tristate are prevented.

An output buffer, said output buffer having an output terminal for coupling to a bus, said output buffer having a first power supply node for coupling to a first power supply voltage, said output buffer also having a second power supply node for coupling to a second power supply voltage lower than said first power supply voltage, said output buffer having a drive mode and a high impedance mode, said output buffer driving said output terminal between substantially said first power supply voltage and said second power supply voltage in said drive mode, said output buffer having a high input impedance at said output terminal in said high impedance mode, said output terminal being driven at a bus voltage in said high impedance state, said bus voltage being capable of exceeding said first voltage, said output buffer comprising:

• a P-channel driver transistor coupled between the first power supply node and said output terminal, said P-channel driver transistor being in an N-well;
• a bias circuit, comprising:
• a sensing circuit having a first state and a second state, said sensing circuit being coupled to the first power supply node and to the output terminal, said sensing circuit switching to said first state when said bus voltage goes below a lower switchover voltage less than the first power supply voltage, said sensing circuit switching to said second state when said bus voltage goes above an upper switchover voltage higher than the first power supply voltage, said upper switchover voltage being more than 0.5 volts above the first power supply voltage, said lower switchover voltage being less than a voltage which is 0.5 volts below the first power supply voltage;
• a switch circuit coupled to said N-well, said first power supply node, and said output terminal, said switch circuit for applying said first power supply voltage to said N-well responsive to said first state of said sensing circuit, said switch circuit for applying said bus voltage to said N-well responsive to said second state of said sensing circuit;
• and
• means for coupling said sensing circuit to said switch circuit;
• wherein said bias circuit has increased stability against bus voltage variations between the lower and upper switchover voltages.

An output buffer, said output buffer having an output terminal for coupling to a bus, said output buffer having a first power supply node for coupling to a first power supply voltage, said output buffer also having a second power supply node for coupling to a second power supply voltage lower than said first power supply voltage, said output buffer having a drive mode and a high impedance mode, said output buffer driving said output terminal between substantially said first power supply voltage and said second power supply voltage in said drive mode, said output buffer having a high input impedance at said output terminal in said high impedance mode, said output terminal being driven at a bus voltage in said high impedance state, said bus voltage being capable of exceeding said first voltage, said output buffer comprising:

• a P-channel driver transistor coupled between the first power supply node and said output terminal, said P-channel driver transistor being in an N-well;
• a bias circuit, comprising:
• a sensing circuit having a first state and a second state, said sensing circuit being coupled to the first power supply node and to the output terminal, said sensing circuit switching to said first state when said bus voltage goes below a lower switchover voltage less than the first power supply voltage, said sensing circuit switching to said second state when said bus voltage goes above an upper switchover voltage higher than the first power supply voltage, said upper switchover voltage being near 3.8 volts, said lower switchover voltage being near 2.3 volts;
• a switch circuit coupled to said N-well, said first power supply node, and said output terminal, said switch circuit for applying said first power supply voltage to said N-well responsive to said first state of said sensing circuit, said switch circuit for applying said bus voltage to said N-well responsive to said second state of said sensing circuit;
• and
• means for coupling said sensing circuit to said switch circuit;
• wherein said bias circuit has increased stability against bus voltage variations between the lower and upper switchover voltages.

An output buffer, said output buffer having an output terminal for coupling to a bus, said output buffer having a first power supply node for coupling to a first power supply voltage, said output buffer also having a second power supply node for coupling to a second power supply voltage lower than said first power supply voltage, said output buffer having a drive mode and a high impedance mode, said output buffer driving said output terminal between substantially said first power supply voltage and said second power supply voltage in said drive mode, said output buffer having a high input impedance at said output terminal in said high impedance mode, said output terminal being driven at a bus voltage in said high impedance state, said bus voltage being capable of exceeding said first voltage, said output buffer comprising:

• a P-channel driver transistor coupled between the first power supply node and said output terminal, said P-channel driver transistor being in an N-well;
• a bias circuit, comprising:
• a sensing circuit having a first state and a second state, said sensing circuit being coupled to the first power supply node and to the output terminal, said sensing circuit switching to said first state when said bus voltage goes below a lower switchover voltage less than the first power supply voltage, said sensing circuit switching to said second state when said bus voltage goes above an upper switchover voltage higher than the first power supply voltage;
• a switch circuit coupled to said N-well, said first power supply node, and said output terminal, said switch circuit for applying said first power supply voltage to said N-well responsive to said first state of said sensing circuit, said switch circuit for applying said bus voltage to said N-well responsive to said second state of said sensing circuit;
• said switch circuit comprising:
• a first transistor coupled between said first power supply node and said N-well and having a control node, said first transistor being turned on in said first state of said sensing circuit and being turned off in said second state of said sensing circuit;
• a second transistor coupled between said output terminal and said N-well and having a control node, said second transistor being turned on in said second state of said sensing circuit and being turned off in said first state of said sensing circuit;
• and
• means for coupling said sensing circuit to said switch circuit;
• wherein said bias circuit has increased stability against bus voltage variations between the lower and upper switchover voltages.

An output buffer, said output buffer having an output terminal for coupling to a bus, said output buffer having a first power supply node for coupling to a first power supply voltage, said output buffer also having a second power supply node for coupling to a second power supply voltage lower than said first power supply voltage, said output buffer having a drive mode and a high impedance mode, said output buffer driving said output terminal between substantially said first power supply voltage and said second power supply voltage in said drive mode, said output buffer having a high input impedance at said output terminal in said high impedance mode, said output terminal being driven at a bus voltage in said high impedance state, said bus voltage being capable of exceeding said first voltage, said output buffer comprising:

• a P-channel driver transistor having a source coupled to the first power supply node and a drain coupled to said output terminal, said P-channel driver transistor being in an N-well;
• an N-well bias circuit for biasing said N-well to a voltage sufficient to prevent forward biasing of said drain with respect to said N-well during said high impedance mode, said N-well bias circuit comprising:
• a latch means;
• a switch circuit coupled to said N-well, said first power supply node, and said output terminal, said switch circuit for engaging said first power supply node to said N-well responsive to a first state of a sensing circuit, said switch circuit for engaging said output terminal to said N-well responsive to a second state of a sensing circuit;
• and
• means for coupling said latch means to said switch circuit;
• whereby said N-well voltage is stabilized against bus voltage variations near said first power supply voltage during said high impedance mode.