State saving and restoration in reprogrammable FPGAs

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions, wherein said registers comprise a block of RAM cells accessed by at least one of said logic blocks;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• state saving means for preventing said configuration means from changing the content of at least some of said registers.

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein a SAVE STATE signal is generated by said field-programmable gate array during a first configuration and prevents said configuration means from configuring during a second configuration following said first configuration.

A field-programmable gate array (FPGA) with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein said state saving means comprises a SAVE STATE signal associated with each block random access memory (RAM) in said FPGA for preventing said configuration means from controlling the state of said block RAM.

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein said state saving means includes means connected to a flip flop in at least one of said logic blocks for preventing said configuration means from changing the content of said flip flop in response to a SAVE STATE signal.

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein said state saving means includes means connected to a memory cell in at least one of said logic blocks for preventing said configuration means from configuring said memory cell in response to a SAVE STATE signal.

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein said state saving means includes means connected to a block RAM accessible to at least one of said logic blocks for preventing said configuration means from changing the content of said block RAM in response to a SAVE STATE signal.

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein a SAVE STATE signal is provided as part of a bitstream controlling said configuration means and prevents said state saving means from configuring at least some of said registers.

A field-programmable gate array with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein said state saving means prevents said configuration means from initializing a flip flop formed as part of one of said logic blocks.

A field-programmable gate array (FPGA) with state saving comprising:

• a plurality of logic blocks for generating logic functions;
• a plurality of registers for storing said logic functions;
• an interconnect structure for interconnecting said logic blocks and said registers;
• configuration means for configuring said logic blocks, registers, and interconnect structure to perform a function selected by a user;
• and
• state saving means for preventing said configuration means from changing the content of at least some of said registers, wherein said state saving means comprises a SAVE STATE signal associated with a type of memory in said FPGA for preventing said configuration means from controlling the states of registers of said type of memory.

In a field-programmable gate array (FPGA) having a structure for configuring said FPGA and a structure for saving states of registers in said FPGA which states are representative of information generated by an earlier configuration of the FPGA, a method of operating said FPGA comprising:

• a) configuring said FPGA;
• b) activating said structure for saving said states;
• and
• c) configuring said FPGA again.

A field-programmable gate array (FPGA) comprising:

• a) a plurality of logic blocks having a first configuration for generating data;
• b) a plurality of memory cells the states of which are representative of data generated by the logic blocks having the first configuration;
• c) an interconnect structure for interconnecting the logic blocks and the memory cells;
• d) a reconfiguration circuit for reconfiguring the logic blocks, memory cells, and interconnect structure to have a second configuration selected by a user;
• and
• e) state saving means for preventing the reconfiguration means from changing the states of at least some of the memory cells, in order to preserve the states representative of data generated by the logic blocks having the first configuration and allow at least some of the logic blocks in the second configuration to use the data generated by the logic blocks of the first configuration.

In a field programmable gate array (FPGA) having a structure for configuring the FPGA and a structure for saving states of registers in the FPGA which states are representative of information generated by an earlier configuration of the FPGA, a method of operating the FPGA comprising:

• a) configuring the FPGA;
• b) generating information using the FPGA and storing state information representative of the generated information;
• c) activating the structure for saving states;
• d) reconfiguring the FPGA;
• and
• e) generating new information using the reconfigured FPGA and the stored state information.